Cypress AutoStore STK17T88 Spécifications

Naviguer en ligne ou télécharger Spécifications pour Réveils Cypress AutoStore STK17T88. Cypress AutoStore STK17T88 Specifications Manuel d'utilisatio

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STK17T88
32K x 8 AutoStore nvSRAM with
Real Time Clock
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-52040 Rev. *C Revised November 25, 2009
Features
nvSRAM Combined With Integrated Real-Time Clock
Functions (RTC, Watchdog Timer, Clock Alarm, Power
Monitor)
Capacitor or Battery Backup for RTC
25, 45 ns Read Access and R/W Cycle Time
Unlimited Read/Write Endurance
Automatic Nonvolatile STORE on Power Loss
Nonvolatile STORE Under Hardware or Software Control
Automatic RECALL to SRAM on Power Up
Unlimited RECALL Cycles
200K STORE Cycles
20-Year Nonvolatile Data Retention
Single 3V +20%, -10% Power Supply
Commercial and Industrial Temperatures
48-Pin 300-mil SSOP Package (RoHS Compliant)
Description
The Cypress STK17T88 combines a 256 Kb nonvolatile static
RAM (nvSRAM) with a full-featured real-time clock in a reliable,
monolithic integrated circuit.
The 256 Kb nvSRAM is a fast static RAM with a nonvolatile
QuantumTrap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the STORE operation). On power up,
data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-time alarms or periodic
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
ROW DECODER INPUT BUFFERS
COLUMN DEC
G
E
W
COLUMN I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
A
13
– A
0
STORE
RECALL
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
V
CC
V
CAP
RTC
MUX
A
14
– A
0
X
1
X
2
INT
V
RTCbat
V
RTCcap
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
A
0
A
1
A
2
A
3
A
4
A
10
Quantum Trap
512 X 512
STATIC RAM
ARRAY
512 X 512
Logic Block Diagram
Not Recommended for New Designs
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Résumé du contenu

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STK17T8832K x 8 AutoStore nvSRAM withReal Time ClockCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Doc

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STK17T88Document Number: 001-52040 Rev. *C Page 10 of 24Figure 10. Software Store/Recall Cycle: E CONTROLLED[13]Software-Controlled STORE/RECALL Cyc

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STK17T88Document Number: 001-52040 Rev. *C Page 11 of 24Hardware STORE CycleFigure 11. Hardware STORE CycleSoft Sequence CommandsFigure 12. Soft Se

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STK17T88Document Number: 001-52040 Rev. *C Page 12 of 24Mode SelectionE W G A14-A0Mode I/O Power NotesH X X X Not Selected Output High Z StandbyL H L

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STK17T88Document Number: 001-52040 Rev. *C Page 13 of 24nvSRAM OperationThe STK17T88 nvSRAM is made up of two functional compo-nents paired in the sa

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STK17T88Document Number: 001-52040 Rev. *C Page 14 of 24Software STOREData can be transferred from the SRAM to the nonvolatilememory by a software ad

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STK17T88Document Number: 001-52040 Rev. *C Page 15 of 24Real Time ClockThe clock registers maintain time up to 9,999 years inone-second increments. T

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STK17T88Document Number: 001-52040 Rev. *C Page 16 of 24If a binary ‘1’ is loaded into the register, only the first 2 minutesof the 64 minute cycle i

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STK17T88Document Number: 001-52040 Rev. *C Page 17 of 24Figure 14. Interrupt Block DiagramInterrupt RegisterWatchdog Interrupt Enable (WIE). When se

Page 10 - STK17T88

STK17T88Document Number: 001-52040 Rev. *C Page 18 of 24RTC Register Map0 - Not implemented, reserved for future use.Default Settings of nonvolatile

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STK17T88Document Number: 001-52040 Rev. *C Page 19 of 24Register Map Detail0x7FFFReal Time Clock – Years D7 D6 D5 D4 D3 D2 D1 D010s Years YearsContai

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STK17T88Document Number: 001-52040 Rev. *C Page 2 of 24ContentsFeatures...

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STK17T88Document Number: 001-52040 Rev. *C Page 20 of 240x7FF7Watchdog TimerD7 D6 D5 D4 D3 D2 D1 D0WDS WDW WDTWDS Watchdog Strobe. Setting this bit t

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STK17T88Document Number: 001-52040 Rev. *C Page 21 of 240x7FF2Alarm – SecondsD7 D6 D5 D4 D3 D2 D1 D0M 10s Alarm Seconds Alarm SecondsContains the ala

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STK17T88Document Number: 001-52040 Rev. *C Page 22 of 24Ordering CodesThese parts are not recommended for new designs.Speed:25 - 25 ns45 - 45 nsPacka

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STK17T88Document Number: 001-52040 Rev. *C Page 23 of 24Package DiagramFigure 15. 48-Pin SSOP (51-85061)51-85061-*CNot Recommended for New Designs[+

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Document Number: 001-52040 Rev. *C Revised November 25, 2009 Page 24 of 24All products and company names mentioned in this document may be the tradem

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STK17T88Document Number: 001-52040 Rev. *C Page 3 of 24Pin ConfigurationsFigure 1. 48-Pin SSOPVSSA14A12A7A6DQ0DQ1VCCDQ2A3A2A1VCAPA13A8A9A11A10DQ7DQ6

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STK17T88Document Number: 001-52040 Rev. *C Page 4 of 24Absolute Maximum RatingsVoltage on Input Relative to Ground...–0.5V to 4.1VVolta

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STK17T88Document Number: 001-52040 Rev. *C Page 5 of 24AC Test ConditionsInput Pulse Levels ...0V to

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STK17T88Document Number: 001-52040 Rev. *C Page 6 of 24RTC DC CharacteristicsFigure 4. RTC Component ConfigurationSymbol ParameterCommercial Industr

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STK17T88Document Number: 001-52040 Rev. *C Page 7 of 24SRAM READ Cycles #1 and #2Figure 5. SRAM READ Cycle #1: Address Controlled[3,4,6]Figure 6. S

Page 23 - 51-85061-*C

STK17T88Document Number: 001-52040 Rev. *C Page 8 of 24SRAM WRITE Cycles #1 and #2Figure 7. SRAM WRITE Cycle #1: W Controlled[7, 8]Figure 8. SRAM W

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STK17T88Document Number: 001-52040 Rev. *C Page 9 of 24AutoStore/Power Up RECALLFigure 9. AutoStore Power Up RECALLNotes9. tHRECALL starts from the

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