Cypress CY14B101NA Manuel d'utilisateur

PRELIMINARYCY14B101LA, CY14B101NA1 Mbit (128K x 8/64K x 16) nvSRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 4

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 10 of 25Note21. CE or WE must be > VIH during address transitions.Figure 7. S

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 11 of 25Figure 9. SRAM Write Cycle #2: CE Controlled [3, 18, 19, 21]Figure 10.

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 12 of 25AutoStore/Power Up RECALLParameters Description20 ns 25 ns 45 nsUnitMin M

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 13 of 25Software Controlled STORE/RECALL CycleParameters[27, 28]Description20 ns

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 14 of 25Hardware STORE CycleParameters Description20ns 25ns 45nsUnitMin Max Min M

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 15 of 25 Truth Table For SRAM OperationsHSB must remain HIGH for SRAM operations.

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 16 of 25Ordering InformationSpeed(ns)Ordering CodePackageDiagramPackage TypeOpera

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 17 of 2525 CY14B101LA-ZS25XCT 51-85087 44-pin TSOP II CommercialCY14B101LA-ZS25XC

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 18 of 2545 CY14B101LA-ZS45XCT 51-85087 44-pin TSOP II CommercialCY14B101LA-ZS45XC

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 19 of 25Part Numbering NomenclatureOption:T - Tape & ReelBlank - Std.Speed:20

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 2 of 25Pinouts Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44 Pin T

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 20 of 25Package Diagrams Figure 16. 44-Pin TSOP II (51-85087)MAXMIN.DIMENSION IN

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 21 of 25Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)Package Diagra

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 22 of 25Figure 18. 48-Pin SSOP (51-85061)Package Diagrams (continued)51-85061 *

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 23 of 25Figure 19. 32-Pin SOIC (51-85127)Package Diagrams (continued)[+] Feedba

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 24 of 25Document History PageDocument Title: CY14B101LA/CY14B101NA 1 Mbit (128K x

Document #: 001-42879 Rev. *B Revised January 29, 2009 Page 25 of 25AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corp

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 3 of 25Figure 3. Pin Diagram - 48-Pin SSOP and 32-Pin SOIC Table 1. Pin Definit

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 4 of 25Device OperationThe CY14B101LA/CY14B101NA nvSRAM is made up of twofunction

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 5 of 25During any STORE operation, regardless of how it is initiated,the CY14B101

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 6 of 25Preventing AutoStoreThe AutoStore function is disabled by initiating an Au

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 7 of 25Maximum RatingsExceeding maximum ratings may impair the useful life of the

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 8 of 25AC Test ConditionsInput Pulse Levels...

PRELIMINARYCY14B101LA, CY14B101NADocument #: 001-42879 Rev. *B Page 9 of 25AC Switching Characteristics ParametersDescription20 ns 25 ns 45 nsUnitCyp