CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V1818-Mbit DDR-II+ SRAM 2-Word BurstArchitecture (2.5 Cycle Read Latency)Cypress Semiconductor Corporatio
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 10 of 27Write Cycle DescriptionsThe write cycle descriptions
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 11 of 27The write cycle descriptions of CY7C1170V18 follows.[
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 12 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs in
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 13 of 27IDCODEThe IDCODE instruction causes a vendor-specific
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 14 of 27TAP Controller State DiagramFigure 2 shows the tap co
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 15 of 27TAP Controller Block DiagramFigure 3. Tap Controller
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 16 of 27TAP AC Switching CharacteristicsThe Tap AC Switching
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 17 of 27Identification Register Definitions Instruction Field
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 18 of 27Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit #
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 19 of 27Power Up Sequence in DDR-II+ SRAM DDR-II+ SRAMs must
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 2 of 27Logic Block Diagram (CY7C1166V18)Logic Block Diagram (
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 20 of 27Maximum RatingsExceeding maximum ratings may shorten
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 21 of 27CapacitanceTested initially and after any design or p
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 22 of 27Switching CharacteristicsOver the operating range[20,
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 23 of 27Switching WaveformRead/Write/Deselect SequenceFigure
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 24 of 27Ordering Information Not all of the speed, package an
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 25 of 27333 CY7C1166V18-333BZC 51-85180 165-Ball Fine Pitch B
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 26 of 27Package DiagramFigure 8. 165-Ball FBGA (13 x 15 x 1.4
Document Number: 001-06620 Rev. *D Revised March 06, 2008 Page 27 of 27QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 3 of 27Logic Block Diagram (CY7C1168V18)Logic Block Diagram (
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 4 of 27Pin ConfigurationsCY7C1166V18 (2M x 8)165-Ball FBGA (1
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 5 of 27Pin Configurations (continued)CY7C1168V18 (1M x 18)165
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 6 of 27Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]Inpu
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 7 of 27ZQ Input Output Impedance Matching Input. This input i
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 8 of 27Functional OverviewThe CY7C1166V18, CY7C1177V18, CY7C1
CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 9 of 27echo clock and follows the timing of any data pin. Thi
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