Cypress CY7C1298H Manuel d'utilisateur télécharger pdf

1-Mbit (64K x 18) Pipelined DCD Sync SRAM

CY7C1298H

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05665 Rev. *B Revised July 5, 2006

Features

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

• 64K × 18-bit common I/O architecture

• 3.3V core power supply (V

)

• 2.5V/3.3V I/O power supply (V

DDQ

)

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous Output Enable

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• “ZZ” Sleep Mode option

Functional Description

[1]

The CY7C1298H SRAM integrates 64K x 18 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and CE

), Burst

Control inputs (ADSC

, ADSP, and ADV), Write Enables

(BW

[A:B]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE

) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP

) or

Address Strobe Controller (ADSC

) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

controlled by the byte write control inputs. GW

active LOW

causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

The CY7C1298H operates from a +3.3V core power supply

while all outputs operate either with a +2.5V or +3.3V supply.

All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

166 MHz 133 MHz Unit

Maximum Access Time 3.5 4.0 ns

Maximum Operating Current 240 225 mA

Maximum CMOS Standby Current 40 40 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

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Page 1 - CY7C1298H

1-Mbit (64K x 18) Pipelined DCD Sync SRAMCY7C1298HCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Docum

Page 2 - 0, A1, A

CY7C1298HDocument #: 38-05665 Rev. *B Page 10 of 16Switching Characteristics Over the Operating Range [14, 15]Parameter Description166 MHz 133 MHzUnit

Page 3

CY7C1298HDocument #: 38-05665 Rev. *B Page 11 of 16Switching WaveformsRead Timing[16]Note: 16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIG

Page 4

CY7C1298HDocument #: 38-05665 Rev. *B Page 12 of 16Write Timing[16, 17]Note: 17. Full width write can be initiated by either GW LOW; or by GW HIGH, BW

Page 5

CY7C1298HDocument #: 38-05665 Rev. *B Page 13 of 16Read/Write Timing[16, 18, 19]Notes: 18. The data bus (Q) remains in High-Z following a WRITE cycle,

Page 6 - Truth Table

CY7C1298HDocument #: 38-05665 Rev. *B Page 14 of 16ZZ Mode Timing[20, 21]Notes: 20. Device must be deselected when entering ZZ mode. See truth table f

Page 7

CY7C1298HDocument #: 38-05665 Rev. *B Page 15 of 16© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change w

Page 8 - Operating Range

CY7C1298HDocument #: 38-05665 Rev. *B Page 16 of 16Document History PageDocument Title: CY7C1298H 1-Mbit (64K x 18) Pipelined DCD Sync SRAMDocument Nu

Page 9 - Capacitance

CY7C1298HDocument #: 38-05665 Rev. *B Page 2 of 16Functional Block DiagramADDRESSREGISTERADVCLKBURSTCOUNTER ANDLOGICCLRQ1Q0ADSCBWBBWACE1DQB, DQPBBYTE

Page 10 - [+] Feedback

CY7C1298HDocument #: 38-05665 Rev. *B Page 3 of 16Pin Configurations100-Pin TQFPTop ViewANCNCVDDQVSSQNCDQPADQADQAVSSQVDDQDQADQAVSSNCVDDZZDQADQAVDDQVSS

Page 11 - Switching Waveforms

CY7C1298HDocument #: 38-05665 Rev. *B Page 4 of 16Pin Descriptions Pin Type DescriptionA0, A1, A Input-SynchronousAddress Inputs used to select one of

Page 12

CY7C1298HDocument #: 38-05665 Rev. *B Page 5 of 16Functional OverviewAll synchronous inputs pass through input registers controlledby the rising edge

Page 13

CY7C1298HDocument #: 38-05665 Rev. *B Page 6 of 16 Interleaved ‘Burst Address Table (MODE = Floating or VDD)First AddressA1, A0SecondAddressA1, A0Thir

Page 14

CY7C1298HDocument #: 38-05665 Rev. *B Page 7 of 16Truth Table for Read/Write[2,3]Function GW BWE BWABWBRead H H X XRead H L H HWrite byte A – (DQA and

Page 15

CY7C1298HDocument #: 38-05665 Rev. *B Page 8 of 16Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Stora

Page 16

CY7C1298HDocument #: 38-05665 Rev. *B Page 9 of 16Capacitance[9]Parameter Description Test Conditions100 TQFPMax. UnitCIN Input Capacitance TA = 25°C,

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