Cypress EZ-OTG CY7C67200 Spécifications

CY7C67200EZ-OTG™ Programmable USBOn-The-Go Host/Peripheral ControllerCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709

CY7C67200Document #: 38-08014 Rev. *H Page 10 of 85Power Savings and Reset DescriptionThe EZ-OTG modes and reset conditions are described in this se

CY7C67200Document #: 38-08014 Rev. *H Page 11 of 85the BIOS ROM, refer to the Programmers documentation and the BIOS documentation.During developmen

CY7C67200Document #: 38-08014 Rev. *H Page 12 of 85CPU Flags Register [0xC000] [R]Figure 7. CPU Flags Register Register Description The CPU Flags r

CY7C67200Document #: 38-08014 Rev. *H Page 13 of 85Bank Register [0xC002] [R/W]Figure 8. Bank Register Register Description The Bank register maps

CY7C67200Document #: 38-08014 Rev. *H Page 14 of 85CPU Speed Register [0xC008] [R/W]Figure 10. CPU Speed Register Register DescriptionThe CPU Speed

CY7C67200Document #: 38-08014 Rev. *H Page 15 of 85Power Control Register [0xC00A] [R/W]Figure 11. Power Control Register Register DescriptionThe P

CY7C67200Document #: 38-08014 Rev. *H Page 16 of 85Setting this bit to ‘1’ immediately initiates HALT mode. While in HALT mode, only the CPU is stop

CY7C67200Document #: 38-08014 Rev. *H Page 17 of 85UART Interrupt Enable (Bit 3)The UART Interrupt Enable bit enables or disables the following UART

CY7C67200Document #: 38-08014 Rev. *H Page 18 of 85USB Diagnostic Register [0xC03C] [R/W]Figure 14. USB Diagnostic Register Register DescriptionThe

CY7C67200Document #: 38-08014 Rev. *H Page 19 of 85Watchdog Timer Register [0xC00C] [R/W]Figure 15. Watchdog Timer Register Register DescriptionThe

CY7C67200Document #: 38-08014 Rev. *H Page 2 of 85ContentsIntroduction ...3Proce

CY7C67200Document #: 38-08014 Rev. *H Page 20 of 85Timer n Register [R/W] Timer 0 Register 0xC010 Timer 1 Register 0xC012Figure 16. Timer n Regis

CY7C67200Document #: 38-08014 Rev. *H Page 21 of 85Register Description The USB n Control register is used in both host and device mode. It monitors

CY7C67200Document #: 38-08014 Rev. *H Page 22 of 85USB Host Only RegistersThere are twelve sets of dedicated registers to USB host only operation. E

CY7C67200Document #: 38-08014 Rev. *H Page 23 of 85Register DescriptionThe Host n Control register allows high-level USB transaction control.Preambl

CY7C67200Document #: 38-08014 Rev. *H Page 24 of 85Host n Count Register [R/W] Host 1 Count Register 0xC084 Host 2 Count Register 0xC0A4Figure 20.

CY7C67200Document #: 38-08014 Rev. *H Page 25 of 85Stall Flag (Bit 7)The Stall Flag bit indicates that the peripheral device replied with a Stall in

CY7C67200Document #: 38-08014 Rev. *H Page 26 of 85Register DescriptionThe Host n PID register is a write-only register that provides the PID and En

CY7C67200Document #: 38-08014 Rev. *H Page 27 of 85Host n Device Address Register [W] Host 1 Device Address Register 0xC088 Host 2 Device Address

CY7C67200Document #: 38-08014 Rev. *H Page 28 of 851: Enable SOF/EOP timer interrupt0: Disable SOF/EOP timer interruptPort A Wake Interrupt Enable (

CY7C67200Document #: 38-08014 Rev. *H Page 29 of 85Port A Wake Interrupt Flag (Bit 6)The Port A Wake Interrupt Flag bit indicates remote wakeup on P

CY7C67200Document #: 38-08014 Rev. *H Page 3 of 85IntroductionEZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first USB On-The-Go (OTG) host/peripher

CY7C67200Document #: 38-08014 Rev. *H Page 30 of 85Host n SOF/EOP Counter Register [R] Host 1 SOF/EOP Counter Register 0xC094 Host 2 SOF/EOP Count

CY7C67200Document #: 38-08014 Rev. *H Page 31 of 85Device n Endpoint n Control Register [R/W] Device n Endpoint 0 Control Register [Device 1: 0x020

CY7C67200Document #: 38-08014 Rev. *H Page 32 of 850: Do not send StallISO Enable (Bit 4)The ISO Enable bit enables and disables an Isochronous tran

CY7C67200Document #: 38-08014 Rev. *H Page 33 of 85Register DescriptionThe Device n Endpoint n Address register is used as the base pointer into mem

CY7C67200Document #: 38-08014 Rev. *H Page 34 of 85Register DescriptionThe Device n Endpoint n Count register designates the maximum packet size tha

CY7C67200Document #: 38-08014 Rev. *H Page 35 of 85IN Exception Flag (Bit 8)The IN Exception Flag bit indicates when the device received an IN packe

CY7C67200Document #: 38-08014 Rev. *H Page 36 of 85Device n Endpoint n Count Result Register [R/W] Device n Endpoint 0 Count Result Register [Devic

CY7C67200Document #: 38-08014 Rev. *H Page 37 of 85Device n Interrupt Enable Register [R/W] Device 1 Interrupt Enable Register 0xC08C Device 2 Int

CY7C67200Document #: 38-08014 Rev. *H Page 38 of 85EP5 Interrupt Enable (Bit 5)The EP5 Interrupt Enable bit enables or disables an endpoint five (EP

CY7C67200Document #: 38-08014 Rev. *H Page 39 of 85Device n Address Register [W] Device 1 Address Register 0xC08E Device 2 Address Register 0xC0AE

CY7C67200Document #: 38-08014 Rev. *H Page 4 of 85USB InterfaceEZ-OTG has two built-in Host/Peripheral SIEs that each have a single USB transceiver,

CY7C67200Document #: 38-08014 Rev. *H Page 40 of 850: Interrupt did not triggerReset Interrupt Flag (Bit 8)The Reset Interrupt Flag bit indicates if

CY7C67200Document #: 38-08014 Rev. *H Page 41 of 85Device n Frame Number Register [R] Device 1 Frame Number Register 0xC092 Device 2 Frame Number

CY7C67200Document #: 38-08014 Rev. *H Page 42 of 85Register DescriptionThe Device n SOF/EOP Count register must be written with the time expected be

CY7C67200Document #: 38-08014 Rev. *H Page 43 of 85D+ Pull-down Enable (Bit 7)The D+ Pull-down Enable bit enables or disables a pull-down resistor o

CY7C67200Document #: 38-08014 Rev. *H Page 44 of 85Register DescriptionThe GPIO Control register configures the GPIO pins for various interface opti

CY7C67200Document #: 38-08014 Rev. *H Page 45 of 85Register DescriptionThe GPIO 0 Output Data register controls the output data of the GPIO pins. Th

CY7C67200Document #: 38-08014 Rev. *H Page 46 of 85Register DescriptionThe GPIO 0 Input Data register reads the input data of the GPIO pins. The GPI

CY7C67200Document #: 38-08014 Rev. *H Page 47 of 85Register DescriptionThe GPIO 0 Direction register controls the direction of the GPIO data pins (i

CY7C67200Document #: 38-08014 Rev. *H Page 48 of 85HSS Control Register [0xC070] [R/W]Figure 48. HSS Control Register Register DescriptionThe HSS C

CY7C67200Document #: 38-08014 Rev. *H Page 49 of 85Transmit Ready (Bit 4)The Transmit Ready bit is a read only bit that indicates if the HSS Transmi

CY7C67200Document #: 38-08014 Rev. *H Page 5 of 85UART Features Supports baud rates of 900 to 115.2K 8-N-1UART PinsI2C EEPROM InterfaceEZ-OTG prov

CY7C67200Document #: 38-08014 Rev. *H Page 50 of 85Register DescriptionThe HSS Baud Rate register sets the HSS Baud Rate. At reset, the default valu

CY7C67200Document #: 38-08014 Rev. *H Page 51 of 85Register DescriptionThe HSS Data register contains data received on the HSS port (not for block r

CY7C67200Document #: 38-08014 Rev. *H Page 52 of 85Register DescriptionThe HSS Receive Counter register designates the block byte length for the nex

CY7C67200Document #: 38-08014 Rev. *H Page 53 of 85Register DescriptionThe HSS Transmit Counter register designates the block byte length for the ne

CY7C67200Document #: 38-08014 Rev. *H Page 54 of 85Register DescriptionThe Interrupt Routing register allows the HPI port to take over some or all o

CY7C67200Document #: 38-08014 Rev. *H Page 55 of 85HPI Swap 0 Enable (Bit 0)Both HPI Swap bits (bits 8 and 0) must be set to identical values. When

CY7C67200Document #: 38-08014 Rev. *H Page 56 of 85HPI Status Port [] [HPI: R] Figure 60. HPI Status Port Register DescriptionThe HPI Status Port p

CY7C67200Document #: 38-08014 Rev. *H Page 57 of 85Done2 Flag (Bit 3)In host mode the Done2 Flag bit is a read-only bit that indicates if a host pac

CY7C67200Document #: 38-08014 Rev. *H Page 58 of 85Register DescriptionThe SPI Configuration register controls the SPI port. Fields apply to both ma

CY7C67200Document #: 38-08014 Rev. *H Page 59 of 85SPI Control Register [0xC0CA] [R/W] Figure 62. SPI Control Register Register DescriptionThe SPI

CY7C67200Document #: 38-08014 Rev. *H Page 6 of 85HSS PinsHost Port Interface (HPI)EZ-OTG has an HPI interface. The HPI interface provides DMA acces

CY7C67200Document #: 38-08014 Rev. *H Page 60 of 85Receive Bit Length (Bits [2:0])The Receive Bit Length field controls whether a full byte or parti

CY7C67200Document #: 38-08014 Rev. *H Page 61 of 85Register DescriptionThe SPI Status register is a read only register that provides status for the

CY7C67200Document #: 38-08014 Rev. *H Page 62 of 85Register DescriptionThe SPI CRC Control register provides control over the CRC source and polynom

CY7C67200Document #: 38-08014 Rev. *H Page 63 of 85SPI Data Register [0xC0D6] [R/W]Figure 68. SPI Data Register Register DescriptionThe SPI Data re

CY7C67200Document #: 38-08014 Rev. *H Page 64 of 85SPI Transmit Count Register [0xC0DA] [R/W] Figure 70. SPI Transmit Count Register Register Descr

CY7C67200Document #: 38-08014 Rev. *H Page 65 of 85Register DescriptionThe SPI Receive Count register designates the block byte length for the SPI r

CY7C67200Document #: 38-08014 Rev. *H Page 66 of 85ReservedAll reserved bits must be written as ‘0’.UART Status Register [0xC0E2] [R]Figure 74. UAR

CY7C67200Document #: 38-08014 Rev. *H Page 67 of 85Pin DiagramThe following describes the CY7C67200 48-pin FBGA.Figure 76. EZ-OTG Pin DiagramPin De

CY7C67200Document #: 38-08014 Rev. *H Page 68 of 85H6 GPIO20/A1 IO GPIO20: General Purpose IOA1: HPI A1F5 GPIO19/A0 IO GPIO19: General Purpose IOA0:

CY7C67200Document #: 38-08014 Rev. *H Page 69 of 85Absolute Maximum RatingsThis section lists the absolute maximum ratings. Stresses above those lis

CY7C67200Document #: 38-08014 Rev. *H Page 7 of 85Component details: D1 and D2: Schottky diodes with a current rating greater than 60 mA. C1: Cera

CY7C67200Document #: 38-08014 Rev. *H Page 70 of 85DC Characteristics Notes6. All tests were conducted with Charge pump off.7. ICC and ICCB values

CY7C67200Document #: 38-08014 Rev. *H Page 71 of 85USB TransceiverUSB 2.0-compatible in full- and low-speed modes. This product was tested as compli

CY7C67200Document #: 38-08014 Rev. *H Page 72 of 85Clock Timing I2C EEPROM Timing Parameter Description Min. Typ. Max. UnitfCLKClock Frequency – 1

CY7C67200Document #: 38-08014 Rev. *H Page 73 of 85Figure 77. HPI (Host Port Interface) Write Cycle Timing Parameter Description Min. Typical Max.

CY7C67200Document #: 38-08014 Rev. *H Page 74 of 85HPI (Host Port Interface) Read Cycle Timing Parameter Description Min. Typ. Max. UnittASUAddress

CY7C67200Document #: 38-08014 Rev. *H Page 75 of 85HSS BYTE Mode Transmit qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the dia

CY7C67200Document #: 38-08014 Rev. *H Page 76 of 85Hardware CTS/RTS HandshaketCTSset-up: HSS_CTS setup time before HSS_RTS = 1.5T min.tCTShold:

CY7C67200Document #: 38-08014 Rev. *H Page 77 of 85Register SummaryTable 42. Register Summary R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit

CY7C67200Document #: 38-08014 Rev. *H Page 78 of 85R/W 0xC024 GPIO 1 Output Data GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000GPIO23 GPIO22 GPIO21

CY7C67200Document #: 38-08014 Rev. *H Page 79 of 85R/W 0xC090 Host 1 Status VBUS InterruptFlagIDInterruptFlagReserved SOF/EOPInterruptFlagReserved x

CY7C67200Document #: 38-08014 Rev. *H Page 8 of 85Crystal InterfaceThe recommended crystal circuit to be used with EZ-OTG is shown in Figure 4. If a

CY7C67200Document #: 38-08014 Rev. *H Page 80 of 85R/W 0xC0D6 SPI Data Port t Reserved xxxx xxxxData xxxx xxxxR/W 0xC0D8 SPI Transmit Address Addres

CY7C67200Document #: 38-08014 Rev. *H Page 81 of 85Ordering InformationOrdering Code DefinitionsTable 43. Ordering InformationOrdering Code Package

CY7C67200Document #: 38-08014 Rev. *H Page 82 of 85Package DiagramFigure 78. 48-ball (7.00 mm × 7.00 mm × 1.2 mm) FBGA BA4851-85096 *I

CY7C67200Document #: 38-08014 Rev. *H Page 83 of 85Acronyms Document ConventionsUnits of Measure Table 44. Acronyms Used in this DocumentAcronym De

CY7C67200Document #: 38-08014 Rev. *H Page 84 of 85Document History PageDocument Title: CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral

Document #: 38-08014 Rev. *H Revised September 21, 2011 Page 85 of 85All products and company names mentioned in this document may be the trademarks

CY7C67200Document #: 38-08014 Rev. *H Page 9 of 85Operational ModesThere are two modes of operation: Coprocessor and Stand-alone.Coprocessor ModeEZ-