Cypress EZ-USB Series 2100 Guide de l'utilisateur

ESCUELA TÉCNICA SUPERIOR DE INGENIEROS INGENIERÍA DE TELECOMUNICACIÓN Especialidad Electrónica de Comunicaciones PROYECTO FINAL DE CARRERA

EZ-USB SX2 Development Kit Manual - Getting StartedPage 16 Rev 2.0 If you plan to download xmaster.hex, you should not “#define NO_RENUM” (which is t

EZ-USB SX2™ Development Kit Manual Page 175.2 Other Firmware ExamplesThe table below describes three firmware examples that show you how to use an ex

EZ-USB SX2 Development Kit Manual - Getting StartedPage 18 Rev 2.0 nector or an external power supply. After code development and debug, the mating p

EZ-USB SX2™ Development Kit Manual Page 196.4 EEPROM Select-Jumper JP4The SX2 chip contains an I²C-compatible “boot load” controller. The boot load c

EZ-USB SX2 Development Kit Manual - Getting StartedPage 20 Rev 2.0 6.5 Interface ConnectorsSix 20-pin headers P1-P6 on the SX2 Development Board hav

EZ-USB SX2™ Development Kit Manual Page 21Tables 4 and 5 show the Pinout for P8 and P9. Table 5. P8 Pinout P8 PinoutPin # Name Description1TV892+5V3

EZ-USB SX2 Development Kit Manual - Getting StartedPage 22 Rev 2.0 Table 6. Pin 9 Pinout P9 PinoutPin # Name Description1+5V23.3V3 SLRD SLRD is the

EZ-USB SX2™ Development Kit Manual Page 236.7 Indicators—Power and StatusLED D1 is connected to the PCB 5 volt supply, which is normally supplied fro

EZ-USB SX2 Development Kit Manual - Getting StartedPage 24 Rev 2.0

Cypress Semiconductor, Personal Communications Division 3901 North First Street San Jose, CA 95134-1599 www.cypress.com EZ-USB SX2 SIEMaster User’s G

Capítulo 1Objetivo y alcance1.1. Justifica ción de la necesidad de este ProyectoGran parte de los sistemas electrónicos que un ingeniero pueda desarrol

Cypress Disclaimer Agreement The information in this document is subject to change without notice and should not be construed as a commitment by C

i Table of Contents 1.0 Purpose ...

ii

SX2 SIEMaster User’s Guide v1.0 Page 1 1.0 Purpose Cypress designed the SIEMaster Utility so that you can examine the basic functions of the E

SX2 SIEMaster User’s Guide Page 2 SX2 SIEMaster User’s Guide v1.0 2.0 Hardware Setup The steps to configure the hardware for use with SIEMaster are

SX2 SIEMaster User’s Guide v1.0 Page 3 3.0 Using SIEMaster SIEMaster’s GUI has seven function areas—Default Enumeration, Custom Enumeration, Int

SX2 SIEMaster User’s Guide Page 4 SX2 SIEMaster User’s Guide v1.0 2. In the Read group box, click on the Read button with the default value 01: IF

SX2 SIEMaster User’s Guide v1.0 Page 5 4. In the Read group box, again click on the Read button with the default value 01: IFCONFIG selected in

SX2 SIEMaster User’s Guide Page 6 SX2 SIEMaster User’s Guide v1.0 3.2 Custom Enumeration SIEMaster allows you to perform a custom enumeration inst

SX2 SIEMaster User’s Guide v1.0 Page 7 1. Start SIEMaster, perform a default enumeration, and clear the EnumOK interrupt. 2. Start Control Pan

10 CAPÍTULO 1. OBJETIVO Y ALCANCEen cambio, Cypress proporciona otro kit de desarrollo, que contiene el integrado EZ-USB SX2 (C7C68001). Pero, incluso

SX2 SIEMaster User’s Guide Page 8 SX2 SIEMaster User’s Guide v1.0 5. Enter the data phase byte count in the Value field adjacent to the selected

SX2 SIEMaster User’s Guide v1.0 Page 9 3.6 Read Setup The Setup group box contains functions for reading USB Control Transfer as well as functio

SX2 SIEMaster User’s Guide Page 10 SX2 SIEMaster User’s Guide v1.0 5. Switch to the Control Panel, change the VendReq direction indicator Dir to

SX2 SIEMaster User’s Guide v1.0 Page 11 3.7 Transfer Endpoint Zero Data SIEMaster contains functions for reading from and writing to Endpoint Ze

SX2 SIEMaster User’s Guide Page 12 SX2 SIEMaster User’s Guide v1.0 4.0 Summary The SIEMaster Utility is a development tool that allows you to easi

SX2 SIEMaster User’s Guide v1.0 Page 13 5.0 Document Revision History Description Title: EZUSB SX2 SIEMaster User’s Guide: A Programming and Tes

EZ-USB SX2™ High-Speed USB Interface DeviceCY7C68001Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Do

CY7C68001Document #: 38-08013 Rev. *H Page 2 of 422.2 IntroductionThe EZ-USB SX2™ USB interface device is designed to workwith any external master, s

CY7C68001Document #: 38-08013 Rev. *H Page 3 of 42• 0xC4: This initial byte tells the SX2 that this is a valid EE-PROM with configuration information

1.3. POSIBLES AMPLIACIONES 11Consideraciones de d iseñ o ele ctrónico.Ambos p untos se dejan para posteriores Proyectos.

CY7C68001Document #: 38-08013 Rev. *H Page 4 of 42or resuming or that a self-powered device has been pluggedin or unplugged. If the SX2 is bus-powere

CY7C68001Document #: 38-08013 Rev. *H Page 5 of 423.6.3 Endpoint Configurations (High-speed Mode) Endpoint 0 is the same for every configuration as i

CY7C68001Document #: 38-08013 Rev. *H Page 6 of 42or 16- bit operation by an internal configuration bit, and anOutput Enable signal SLOE enables the

CY7C68001Document #: 38-08013 Rev. *H Page 7 of 423.7.8 Command ProtocolAn address of [1 0 0] on FIFOADR [2:0] will select thecommand interface. The

CY7C68001Document #: 38-08013 Rev. *H Page 8 of 424.0 EnumerationThe SX2 has two modes of enumeration. The first mode isautomatic through EEPROM boo

CY7C68001Document #: 38-08013 Rev. *H Page 9 of 42PKTEND pin does not apply to Endpoint 0. The only way tosend a short or zero length packet is by wr

CY7C68001Document #: 38-08013 Rev. *H Page 10 of 42In order to read the status of this register, the external mastermust do the following sequence of

CY7C68001Document #: 38-08013 Rev. *H Page 11 of 426.2 56-pin QFN CY7C6800156-pin QFNGNDVCCGNDDMINUSSLWRDPLUSVCCAGNDSLRDAVCCXTALINXTALOUTIFCLKRESERVE

CY7C68001Document #: 38-08013 Rev. *H Page 12 of 426.3 CY7C68001 Pin DefinitionsTable 6-1. SX2 Pin DefinitionsQFNPinSSOPPin Name Type Default Descri

CY7C68001Document #: 38-08013 Rev. *H Page 13 of 421 8 SLRD Input N/A SLRD is the input-only read strobe with programmable polarity (POLAR.3) for the

12 CAPÍTULO 1. OBJETIVO Y ALCANCE

CY7C68001Document #: 38-08013 Rev. *H Page 14 of 427.0 Register SummaryTable 7-1. SX2 Register SummaryHex Size Name Description D7 D6 D5 D4 D3 D2 D

CY7C68001Document #: 38-08013 Rev. *H Page 15 of 427.1 IFCONFIG Register 0x017.1.1 Bit 7: IFCLKSRCThis bit selects the clock source for the FIFOs. If

CY7C68001Document #: 38-08013 Rev. *H Page 16 of 42These flags can be programmed to represent various FIFOflags using four select bits for each FIFO.

CY7C68001Document #: 38-08013 Rev. *H Page 17 of 42b. Command data write of upper nibble of the High Byte of Register Address (0x0E)c. Command data w

CY7C68001Document #: 38-08013 Rev. *H Page 18 of 42In addition, the EPxPKTLENH register has four other endpointconfiguration bits. 7.6.1 Bit 7: IN

CY7C68001Document #: 38-08013 Rev. *H Page 19 of 427.7.1 DECIS: EPxPFH.7If DECIS = 0, then PF goes high when the byte count i is equalto or less than

CY7C68001Document #: 38-08013 Rev. *H Page 20 of 427.10 INPKTEND/FLUSH Register 0x20This register allows the external master to duplicate thefunction

CY7C68001Document #: 38-08013 Rev. *H Page 21 of 42descriptor RAM in nibble format. For complete details, refer toSection 4.0.7.16 EP0BUF Register 0x

CY7C68001Document #: 38-08013 Rev. *H Page 22 of 4211.2 Command Interface11.2.1 Command Synchronous Read Table 11-1. Command Synchronous Read Para

CY7C68001Document #: 38-08013 Rev. *H Page 23 of 4211.2.2 Command Synchronous Write Table 11-3. Command Synchronous Write Parameters with Internal

Capítulo 2Estructura de la MemoriaCon la intención de servir de ayuda al diseñ a dor que desee conseguir, en el me-nor tiempo posible, que el sistema

CY7C68001Document #: 38-08013 Rev. *H Page 24 of 4211.2.3 Command Asynchronous Read 11.2.4 Command Asynchronous Write Table 11-5. Command Read Para

CY7C68001Document #: 38-08013 Rev. *H Page 25 of 4211.3 FIFO Interface11.3.1 Slave FIFO Synchronous Read IFCLKSLRDFLAGSSLOEtSRDtRDHtOEontXFDtXFLGDA

CY7C68001Document #: 38-08013 Rev. *H Page 26 of 4211.3.2 Slave FIFO Synchronous Write Table 11-9. Slave FIFO Synchronous Write Parameters with In

CY7C68001Document #: 38-08013 Rev. *H Page 27 of 4211.3.3 Slave FIFO Synchronous Packet End Strobe There is no specific timing requirement that nee

CY7C68001Document #: 38-08013 Rev. *H Page 28 of 42Figure 11-8 shows a scenario where two packets are beingcommitted. The first packet gets committed

CY7C68001Document #: 38-08013 Rev. *H Page 29 of 4211.3.6 Slave FIFO Asynchronous Write 11.3.7 Slave FIFO Asynchronous Packet End Strobe Table 11-1

CY7C68001Document #: 38-08013 Rev. *H Page 30 of 4211.3.8 Slave FIFO Asynchronous Address 11.4 Slave FIFO Address to Flags/Data Following timing is

CY7C68001Document #: 38-08013 Rev. *H Page 31 of 4211.6 Sequence Diagram11.6.1 Single and Burst Synchronous Read Example Figure 11-16 shows the tim

CY7C68001Document #: 38-08013 Rev. *H Page 32 of 4211.6.2 Single and Burst Synchronous Write Figure 11-18 shows the timing relationship of the SLAVE

CY7C68001Document #: 38-08013 Rev. *H Page 33 of 4211.6.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 11-19 diagrams the timing r

14 CAPÍTULO 2. ESTRU CTURA DE LA MEMO RIA3. También como anexo, se adjuntan distintas notas de aplicación en la Parte II.

CY7C68001Document #: 38-08013 Rev. *H Page 34 of 4211.6.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 11-21 diagrams the timing

CY7C68001Document #: 38-08013 Rev. *H Page 35 of 4210, //Descriptor length6, //Descriptor type0x00,0x02, //Specification Version (BCD)00, //Device cl

CY7C68001Document #: 38-08013 Rev. *H Page 36 of 42//Endpoint Descriptor7, //Descriptor length5, //Descriptor type0x88, //Endpoint number, and direct

CY7C68001Document #: 38-08013 Rev. *H Page 37 of 427, //Descriptor length5, //Descriptor type0x88, //Endpoint number, and direction2, //Endpoint type

CY7C68001Document #: 38-08013 Rev. *H Page 38 of 42from the thermal pad to the PCB inner ground plane by a 5 x5 array of via. A via is a plated throu

CY7C68001Document #: 38-08013 Rev. *H Page 39 of 4215.0 Ordering Information16.0 Package Diagrams16.1 56-pin SSOP PackageTable 15-1. Ordering Info

CY7C68001Document #: 38-08013 Rev. *H Page 40 of 42© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change

CY7C68001Document #: 38-08013 Rev. *H Page 41 of 42Document History Page Description Title: CY7C68001 EZ-USB SX2™ High-Speed USB Interface DeviceDocu

CY7C68001Document #: 38-08013 Rev. *H Page 42 of 42*D 130447 12/17/03 KKU Replaced package diagram in Figure 16-2 spec number 51-85144 with clear ima

Revision August 1, 2002Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600August 1, 2002CY3682 Design No

Capítulo 3Introducción a la arquitectura yprotocolo del Bus Serie Universal3.1. Introduc ciónComenzaremos en este capítulo proporcionando unas nocione

CY3682 Design Notes2Revision : August 1, 20021718 WriteDescriptor(); //Load entire descriptor into SX21920 #endif2122 while (!enum_ok); //Wait until

CY3682 Design Notes3Revision : August 1, 2002Figure 1. SX2 Initialization From Reset to DescriptorFigure 2. SX2 Initialization Continued

CY3682 Design Notes4Revision : August 1, 2002WriteRegisterThe WriteRegister function calls the hardware specific func-tion low_level_command_write. T

CY3682 Design Notes5Revision : August 1, 2002Figure 4. Read Register SequenceInterrupt Service RoutineThe Interrupt Service Routine distinguishes bet

CY3682 Design Notes6Revision : August 1, 200280 case 0x04: //Enumeration complete81 enum_ok = TRUE;82 break;83 case 0x20: //Flags84 got_out_data = TR

CY3682 Design Notes7Revision : August 1, 2002To complete endpoint zero data transfers, the ep0buf_readyflag is used. If the SX2 receives a setup requ

CY3682 Design Notes8Revision : August 1, 2002163 else164 WriteRegister (0x32, 0xFF); //Stall the request165 break;166 }167 break;168 case 0x03: // **

CY3682 Design Notes9Revision : August 1, 2002227 case 0xAB:228 if (setuplength > 64) //We want to handle vendor 0xAB229 WriteRegister (0x32, 0xFF)

CY3682 Design Notes10Revision : August 1, 2002Figure 5. Setup Interrupt and AckFigure 6. Setup and EP0 Interrupts and DataData LoopbackIf there is bu

CY3682 Design Notes11Revision : August 1, 2002This is a very simple data loopback example and can be ex-ercised using the EZ-USB Control Panel PC pro

16 CAPÍTULO 3. INTRODUCCIÓN A LA ARQUITECTURA USB5. Modelo de flujo de comunicaciones USB.6. Transferencias, IRPs, tramas y paquetes.7. Transferencias

CY3682 Design Notes© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconduc

Errata Revision: *CAugust 16, 2005Errata Document for CY7C68001 EZ-USB SX2™Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA

CY7C68001ERRATA DOCUMENT © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Sem

CY7C68001 ERRATA DOCUMENT3Document History PageDocument Title: CY7C68001 EZ-USB SX2 Rev E ErrataDocument Number: 38-17011REV. ECN NO. Issue DateOrig.

User guide for EZ-USB Control PanelUser guide for EZ-USB Control Panel.An Overview of the EZ-Usb Control Panel.The EZ_USB Control Panel allows the use

The Application Toolbar.The Application Toolbar has standard buttons such as Cut, Copy, Paste, Save, and Print, as well as an“About” button to get Ver

The Properties Dialog.The General Page.The Verbose Mode option allows the user to select a more verbose output from the content of transferredmessages

Exiting the Program.When the User exits by selecting "File/Exit" or by pressing the "x" in the upper right corner, the user maybe

View Menu Commands.{menuview.gif}Window Menu Commands.{menuwind.gif}Options Menu Commands.{menuopt.gif}Tools Menu Commands.{tools.gif}The tools menu w

3.3. CARACTERÍSTICAS BÁ SICAS DEL USB 17Trama: Intervalo de 1 ms (125 µs en modo high-speed, donde hablaremos d emicrotramas).Transacción: Agrupación

Unary Operations ToolBar.{tbuna.gif}The Unary Operations need no parameters (except the possible selection of a target file).There are several such op

Isochronous Transfer ToolBar.{tbiso.gif}The Isochronous Transfer parameters are entered here.The overall size of an Iso transfer is limited to 1MB.Whe

File Trans..: The File Transfer button allows you to select ISO or BULK endpoints as targets of a file basedoperation. When this button is pressed, Yo

Capítulo 9Notas de aplicaciónSeguidamente recogemos algunas de las notas de aplicación de mayor interéspara el chip SX2:1. SX2 Pr imer (Life After Enu

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 13, 2004SX2 Primer (Life After Enumerat

SX2 Primer (Life After Enumeration) 2purpose for this is to verify that the correct data value waswritten during a command write sequence. Figure 2 s

SX2 Primer (Life After Enumeration) 32. Write 512 bytes into the FIFO (EP6 or EP8) from the external master.3. On the "Bulk Trans" bar of t

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600October 14, 2003, rev. 0.BEZ-USB FX2™/AT2™/SX2™Reset an

18 CAPÍTULO 3. INTRODUCCIÓN A LA ARQUITECTURA USBTransferencias de d atos rápidas y fiables. La fiabilida d del U SB se debe tantoal hardware como a los

EZ-USB FX2™/AT2™/SX2™Reset and Power Considerations2Self-powered hubs will create even shorter pulses on VBUSwhen they are plugged into a host or when

EZ-USB FX2™/AT2™/SX2™Reset and Power Considerations3The easiest solution is to set the DISCON bit to 0, so yourdevice will pull up D+ immediately. See

Revision: 1.0 April 2001Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600April 6, 2001USB Error Handlin

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600December 10, 2002High-speed USB PCB Layout Recommendati

High-speed USB PCB Layout Recommendations2Typical 62-mil, 4-layer PCB ExampleThe recommended stackup for a standard 62-mil (1.6-mm)thick PCB is shown

High-speed USB PCB Layout Recommendations3USB PeninsulaIf the location of a USB connector is near the edge of the PCB,consider placing it on a ‘USB Pe

High-speed USB PCB Layout Recommendations© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without noti

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600January 7, 2002Bulk Transfers with the EZ-USB SX2™ Con

3.3. CARACTERÍSTICAS BÁ SICAS DEL USB 19del sistema operativo imp lica la inclusión de drivers de clase que permitan alos programadores de aplicacione

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface2• Endpoint 6 is programmed for:—IN direction— Double buffering— 512-byt

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface3— Burst Mode with Level Timing— Throttle bursts on Data Request (DREQ0#

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface4Connection DiagramFigure 1 shows the complete set of signal connections

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface5Writing Commands to the SX2There are two types of Command Write sequenc

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface6Reading Status from the SX2The SX2 INT pin provides the SH3 with two si

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface7Reading OUT Packet Data from SX2 Endpoint BufferThe SH3 allocates the a

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface8Writing IN Packet Data to SX2 Endpoint BufferThe SH3 allocates the addr

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface9a. IFCLKSRC = 0 - external clock sourceb. 3048MHZ = 0 - ignored for ext

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface10ii. PL [7:0] = 0000 0000b - Least significant byte of 512-byte packet

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface1120.Set SH3 DMA Channel0 for read bursts to SX2:a. Set transfer count (

20 CAPÍTULO 3. INTRODUCCIÓN A LA ARQUITECTURA USB3.4. Componentes del busLos componentes físicos del Bus Serie U ni versal son los circuitos, conector

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface12DREQ0# Waveform Generation with FLAGBOUT Packet Read BurstsThe FLAGB l

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface13IN Packet Write BurstsThe FLAGB line is also used to create a waveform

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface14Bulk Loopback Sample Descriptors//Device Descriptor18, // Descriptor L

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface150x00,// Maximum Packet Size (LSB)0x02,// Maximum Packet Size (MSB)0, /

Bulk Transfers with the EZ-USB SX2™ connected to an Hitachi SH3™ DMA Interface© Cypress Semiconductor Corporation, 2003. The information contained her

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600September 9, 2003, rev. 0.ABulk Transfers with the EZ-U

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface2— On FLAGB high (FIFO not empty) throttle DMA on until FLAGB low— On F

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface3Connection DiagramFigure 1 shows the complete set of signal connection

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface4Writing Commands to the SX2There are two types of command write sequen

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface5Reading Status from the SX2The SX2 INT pin provides the XScale with t

3.6. MODELO DE COMUNICACIONES US B 21Proporcionar alimentación.Intercambiar datos entre periféricos.El trabajo del host no es trivial. Por suerte, el

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface6Reading OUT Packet Data from SX2 Endpoint BufferThe XScale begins allo

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface7Writing IN Packet Data to SX2 Endpoint BufferThe XScale begins allocat

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface8g. FLAGD/CS# = 1 – use Flag D as chip selecth. DISCON = 0 – to remain

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface917.Program FIFO Empty (EF) Flags (POLAR register) for normal polarity

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface10DREQ0 Waveform Generation with FLAGBOUT Packet Read BurstsThe FLAGB l

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface11IN Packet Write BurstsThe FLAGB line is also used to create a wavefor

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface12Bulk Loopback Sample Descriptors//Device Descriptor18, // Descriptor

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface130x00,// Maximum Packet Size (LSB)0x02,// Maximum Packet Size (MSB)0,

Bulk Transfers with the EZ-USB SX2™ Connectedto an Intel XScale™ DMA Interface143, // Descriptor Type – String 'C', 0,'Y', 0,&apo

Bibliografía[1] Roger S. Pressman. Ingeniería del Software—Un enfoque práctico. McGraw-Hill,sexta edición, 2006.[2] Joseph Schmuller. Sams Teach Yours

22 CAPÍTULO 3. INTRODUCCIÓN A LA ARQUITECTURA USB2. Los drivers cliente USB proporcionan una mem oria buffer utilizada para al-macenar datos cuando se

3.8. TRANSFERENCIAS BULK 23bancho de banda depende de la latencia requerida por el dispositivo (como es espe-cificada en los descriptores del dispositi

24 CAPÍTULO 3. INTRODUCCIÓN A LA ARQUITECTURA USBSoportan detección y recuperación ante errores.

Capítulo 4Descripción del kit4.1. Introduc ción al kit d e desarrollo CY36 8 2El kit de d esarrollo CY3682 proporciona un entorno de desarrollo para d

26 CAPÍTULO 4. DESCRIPCIÓN DEL K IT• Driver d el dispositivo de propósito general EZ-USB.• C ódigo d e muestra del firmware 8051.• Utilidad de panel de

4.2. DESCRIPC IÓN DEL EZ-USB SX2 27Figura 4.1: Diagrama de bloques de la placa EZ-USB SX2.Firmware de ejemplo para el p rocesador e xterno,Esquemas PC

PROYECTO FINAL DE CARRERA:Evaluación del chip EZ-USB SX2 conimplementación de transferencia bulkUSB 2.0Autor: Alejandro Raigón MuñozTutor del Proyecto

28 CAPÍTULO 4. DESCRIPCIÓN DEL K IT

Capítulo 5Probando el kit de desarrollo paso apaso5.1. Introduc ciónEn este capítulo anali z aremos los siguientes aspectos:1. Requisitos previos para

30 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASOAdemás del material proporcionado por el kit de desarrollo, se requiere que e l PCsobre el cua

5.2. REQUISITOS PREVIOS 31Figura 5.1: Comprobando la presencia de controlador host USB 2.0.

32 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASO5.3. Instalac i ón del Panel de Control EZ-USB, Driversy DocumentaciónEl entorno d e desarroll

5.4. TEORÍA DE FUNCIONAM IE NTO DEL KIT DE DESARROLLO 33Figura 5.2: Diagrama de bloques del sistema en Modo 1A.a) En la placa SX2:JP3 conectado entre

34 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASOFigura 5.3: Ventana del Administrador de Dispositivos en modo 1A.

5.4. TEORÍA DE FUNCIONAM IE NTO DEL KIT DE DESARROLLO 35Figura 5.4: E l dispositivo de prueba ha sido conectado a un hub raíz USB 2.0.como se verá lue

36 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASOFigura 5.5: Respuesta de la SX2 al comando de petición de descriptor.escribir firmware. Así, el

5.4. TEORÍA DE FUNCIONAM IE NTO DEL KIT DE DESARROLLO 37Figura 5.6: Diagrama de bloques del sistema en modo 1B.JP8 no conectado (la EEPROM es de 8 kil

38 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASOFigura 5.7: Ventana del A dministrador de Dispositivos de Windows mostrando los dispositivos U

5.4. TEORÍA DE FUNCIONAM IE NTO DEL KIT DE DESARROLLO 39Figura 5.8: Propiedades de “Cypress EZ-USB Sample Device”.botón “Enumerate”, con lo que obtene

40 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASO(a)(b)Figura 5.9: (a) Ventana del Administrador de Dispositivos de Windows mostrando los dispo

5.4. TEORÍA DE FUNCIONAM IE NTO DEL KIT DE DESARROLLO 41Figura 5.10: Transferencia de un descriptor personalizado mediante el SIEMaster.Partiendo del

42 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASOFigura 5.11: Generación de una petición específica de vendedor desde el Panel de Control EZ-U S

5.4. TEORÍA DE FUNCIONAM IE NTO DEL KIT DE DESARROLLO 43Figura 5.12: Leyendo los datos de configuración de una sola vez.Figura 5.13: Escritura d e un v

44 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASOFigura 5.14: Recepción de los 16 bytes de datos de la fase de configuración.Figura 5.15: Genera

5.4. TEORÍA DE FUNCIONAM IE NTO DEL KIT DE DESARROLLO 45Figura 5.16: Leyendo la petición específica de vendedor de salida.7. Pulsando de nuevo en el bo

46 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASOFigura 5.17: Diagrama de bloques del modo 2.5.5. Practica ndo con el kit de desarrollo5.5.1. E

5.5. PRACTICAN DO CON EL KIT DE DESARROLLO 475.5.2. Ejercicio 8—Segunda solución al pr oblema de “Dispositivodesconocido”. Descarga del firmware xmast

Índice generalI Memoria 71. Objetivo y alcance 91.1. Justificación de la necesidad de este Proyecto . . . . . . . . . . . . . . 91.2. Objetivos y alcan

48 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASOFigura 5.18: Borrado de la EEPROM d e 8 kB con la ayuda del firmware vend_ax.hex.6. Pulsamos en

5.5. PRACTICAN DO CON EL KIT DE DESARROLLO 49Figura 5.19: Ruta de datos implementada por el ejemplo xmaster de la SX2.5.5.4. Ejercicio 10—Ejemplo de l

50 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASOFigura 5.20: Configuración de los parámetros del bulkloop.bimos “512”. En este momento, la pant

5.5. PRACTICAN DO CON EL KIT DE DESARROLLO 51ro con 2 bytes. Limpia remos el área de salida de información pulsando en elbotón “Clear”.4. A continuaci

52 CAPÍTULO 5. PROBANDO EL KIT DE DESARROLLO PASO A PASO

Capítulo 6Marco de trabajo para la programaciónUSB6.1. Introduc ciónEn el capítulo anterior analizamos paso a paso el kit de desarrollo CY3682, siem-p

54 CAPÍTULO 6. MARCO DE TRABAJO PARA LA PROGRAMACIÓN USBFigura 6.1: Diagrama de bloques del sistema EZ-USB final.ningún otro driver, a menos que se des

6.2. PROGRAMA CIÓN DEL DRIVER 55c) Russinovich, Mark E., and Solomon, David A. Microsoft Windows Internals,Fourth Edition, http://www.microsoft.com/MS

56 CAPÍTULO 6. MARCO DE TRABAJO PARA LA PROGRAMACIÓN USB2) Architecture of the User-Mode Driver Fr amework,http://www.microsoft.com/whdc/driver/wdf/UM

6.4. ALTERNATIVAS PARA LA CODIFICACIÓN DE LA COMUNICACIÓN USBENTRE LA APLICACIÓN HOST Y EL DISPOSITIVO USB 2.0 57que se pueda compilar en un formato c

4 ÍNDICE GENERAL5.4.2. Ejercicio 4—Estableciendo el entorno de desarrollo para el SIE-Master. Modo 1B . . . . . . . . . . . . . . . . . . . . . . . .

58 CAPÍTULO 6. MARCO DE TRABAJO PARA LA PROGRAMACIÓN USB1. Se trata de un funcionamiento a bajo nivel, es decir, se requiere un controlabsoluto de los

6.5. INSTALANDO EL ESTUDIO DE DESARROLLO USB CY4604 596.5. Instalan do el estudio de desarroll o USB C Y4604La instalación no presenta ninguna dificult

60 CAPÍTULO 6. MARCO DE TRABAJO PARA LA PROGRAMACIÓN USBEl firmware xmaster.hex cargado en la RAM de la FX, yEl identificador de dispositivo “Cypress EZ

6.6. USANDO LA API DE CYPRE SS—CYAPI 61Figura 6.2: Cambiando el controlador de la EZ-USB SX2.6.6.2. Ejercicio 13— Sust i tución de las cadenas de text

62 CAPÍTULO 6. MARCO DE TRABAJO PARA LA PROGRAMACIÓN USB3. Seleccione “No por el momento” y pulse en “Siguiente”.4. Seleccione “Instalar desde una lis

6.6. USANDO LA API DE CYPRE SS—CYAPI 63de e ntrada (hacia el PC), implementaremos una comunicación USB 2.0 entre unaaplicación host y el chip EZ-USB S

64 CAPÍTULO 6. MARCO DE TRABAJO PARA LA PROGRAMACIÓN USBFigura 6.4: Valores de las propiedades del objeto USBDevice al obtener el manejador desde el d

6.6. USANDO LA API DE CYPRE SS—CYAPI 65(a) (b)Figura 6.6: (a) Ventana de variables locales en modo depuración antes de iniciar la transferencia alendp

66 CAPÍTULO 6. MARCO DE TRABAJO PARA LA PROGRAMACIÓN USB//---------------------------------------------------------------------------// PROYECTO FINAL

6.6. USANDO LA API DE CYPRE SS—CYAPI 67AnsiString stringAux; // Variable auxiliar// Limpiamos el área de dibujo inicialCanvas->FillRect(destArea);/

ÍNDICE GENERAL 57.3. El estudio de desarrollo USB CY4604 . . . . . . . . . . . . . . . . . . . 737.4. Documentación del WDK de Microsoft . . . . . . .

68 CAPÍTULO 6. MARCO DE TRABAJO PARA LA PROGRAMACIÓN USBbitmap->LoadFromFile("target.bmp"); // lo cargamos en el bitmapCanvas->Stretch

6.6. USANDO LA API DE CYPRE SS—CYAPI 69Figura 6.7: Formulario principal de la aplicación práctica de una comunicación US B 2.0 tipo bulk conel chip EZ

70 CAPÍTULO 6. MARCO DE TRABAJO PARA LA PROGRAMACIÓN USB6.7. Conclus ionesA pesar de los d efectos, me n cionados con anterioridad, acerca de la mala

Capítulo 7Contenido del CD-ROMSe proporciona, conjuntamente con esta Memoria, un CD-ROM con informaciónde utilidad para el desarrollador. En el CD-ROM

72 CAPÍTULO 7. CONTENIDO DEL CD -R OM6. User guide for EZ-USB Control Panel [EzMrUser.pdf]7. EZ-USB General Purpose Driver Specification [EZ-USB Genera

7.3. EL ESTUDIO DE DESARRO LLO USB CY4604 73Esta nota de aplicación detalla las guías para diseñar una PCB paraUSB high-speed con cuatro capas e imped

74 CAPÍTULO 7. CONTENIDO DEL CD -R OMIntroduction To The Windows Driver Kit: A Comprehensive DriverDevelopment Solution [DEV041_WH06.ppt]Architecture

Parte IIAnexos

Capítulo 8Manuales de referenciaA continuación se recogen los siguientes manuales para facilitar la consulta deinformación:1. EZ-USB SX2–Getting Start

6 ÍNDICE GENERAL

• Cypress Semiconductor • Personal Communication Division • • 3901 North First Street • San Jose, CA 95134 • (408) 943-2600 •• www.cypress.com •EZ-USB

Cypress Disclaimer AgreementThe information in this document is subject to change without notice and should not be con-strued as a commitment by Cypr

iTable of Contents1.0 EZ-USB SX2 Development Kit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Intr

iiTable of Contents

EZ-USB SX2™ Development Kit Manual Page 1Getting Started1.0 EZ-USB SX2 Development Kit Overview1.1 IntroductionThe Cypress EZ-USB SX2 interface dev

EZ-USB SX2 Development Kit Manual - Getting StartedPage 2 Rev 2.0 1.2 Tools1.2.1 Required Tools IncludedThe following list shows the components sup

EZ-USB SX2™ Development Kit Manual Page 32.0 EZ-USB SX2 Development Kit ContentsThe EZ-USB SX2 Development Kit provides a complete hardware and soft

EZ-USB SX2 Development Kit Manual - Getting StartedPage 4 Rev 2.0 3.0 EZ-USB SX2 Development Kit Theory of Operation3.1 Final EZ-USB System Block

EZ-USB SX2™ Development Kit Manual Page 53.2 SX2 Development Kit Theory of OperationIn order to demonstrate the functionality of the SX2, the develop

Parte IMemoria

EZ-USB SX2 Development Kit Manual - Getting StartedPage 6 Rev 2.0 3.2.2 Mode 1B — SIEMaster ModeThe SIEMaster utility uses Mode 1B (see Figure 3). T

EZ-USB SX2™ Development Kit Manual Page 73.2.3 Mode 2 — Development ModeIn Mode 2 (see Figure 4), the SX2 board is unplugged from the FX board. All o

EZ-USB SX2 Development Kit Manual - Getting StartedPage 8 Rev 2.0 3. Windows Millennium4. Windows 98 Second Edition To quickly determine if USB suppo

EZ-USB SX2™ Development Kit Manual Page 93. Move your cursor over the USB bullet. There should be a pop-up that contains two more options. Click on th

EZ-USB SX2 Development Kit Manual - Getting StartedPage 10 Rev 2.0 3. In order to allow the SX2 to be seen by the PC and be controlled by the 8051 pr

EZ-USB SX2™ Development Kit Manual Page 11“Clear” button. The “GetDev” button may be clicked anytime, as many times as you wish. The fol-lowing should

EZ-USB SX2 Development Kit Manual - Getting StartedPage 12 Rev 2.0 5. Start the SIEMaster utility by selecting Start\Programs\Cypress\USB\SX2 SIEMast

EZ-USB SX2™ Development Kit Manual Page 13Figure 5. SX2 Xmaster Example Data Path5.1.1 Running the Loopback Example Firmware (Xmaster - External Mast

EZ-USB SX2 Development Kit Manual - Getting StartedPage 14 Rev 2.0 5. Run C:\CYPRESS\USB\Bin\bulkloop.exe. This is a general-purpose USB data loopbac

EZ-USB SX2™ Development Kit Manual Page 155.1.2 Further Development with the Xmaster Loopback ExampleThe source code for the xmaster firmware example