Cypress CY7C68033 Manuel d'utilisateur

EZ-USB NX2LP-Flex™ Flexible USB NAND Flash ControllerCY7C68033/CY7C68034Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 10 of 33Default High-Speed Alternate SettingsExternal FIFO InterfaceArchitectureThe NX2LP-Flex

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 11 of 33the default NAND firmware image implements an 8-bit databus and up to 8 chip enable pin

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 12 of 33Pin AssignmentsFigure 9 and Figure 10 identify all signals for the 56-pinNX2LP-Flex pac

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 13 of 33Figure 10. CY7C68033/CY7C68034 56-pin QFN Pin AssignmentCY7C68033/CY7C6803456-pin QFN28

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 14 of 33Table 8. NX2LP-Flex Pin Descriptions[6]56 QFN Pin NumberDefault Pin NameNAND Firmware U

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 15 of 3313 GPIO8 GPIO8 I/O/Z I GPIO8: is a bidirectional IO port pin.14 Reserved# N/A Input N/A

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 16 of 3339 PA6 or PKTENDGPIO0(Input)I/O/Z I(PA6)Multiplexed pin whose function is selected by t

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 17 of 3346 PD1 orFD[9]CE1# I/O/Z I(PD1)Multiplexed pin whose function is selected by the IFCONF

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 18 of 33Register SummaryNX2LP-Flex register bit definitions are described in the EZ-USB TRM in

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 19 of 33E629 1 ECCRESET ECC Reset x x x x x x x x 00000000 WE62A 1 ECC1B0 ECC1 Byte 0 Address L

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 2 of 33Default NAND Firmware Features Because the NX2LP-Flex™ is intended for NANDFlash-based U

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 20 of 33E65B 1 NAKIRQ[8]Endpoint Ping-NAK/IBN Interrupt RequestEP8 EP6 EP4 EP2 EP1 EP0 0 IBN xx

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 21 of 33E69E 2 reservedE6A0 1 EP0CS Endpoint 0 Control and StatusHSNAK 0 0 0 0 0 BUSY STALL 100

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 22 of 33E6CD 1 FLOWSTBPERIOD Master-Strobe Half-PeriodD7 D6 D5 D4 D3 D2 D1 D0 00000010 RWE6CE 1

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 23 of 3383 1 DPH0 Data Pointer 0 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW84 1 DPL1[9]Data Po

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 24 of 33Absolute Maximum RatingsStorage Temperature ...–65°C to

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 25 of 33DC CharacteristicsUSB TransceiverUSB 2.0-compliant in full- and high-speed modes.AC Ele

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 26 of 33Slave FIFO Asynchronous ReadFigure 11. Slave FIFO Asynchronous Read Timing Diagram[13]S

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 27 of 33Slave FIFO Asynchronous Packet End StrobeFigure 13. Slave FIFO Asynchronous Packet End

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 28 of 33Slave FIFO Asynchronous AddressFigure 16. Slave FIFO Asynchronous Address Timing Diagra

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 29 of 33Figure 17 diagrams the timing relationship of the SLAVE FIFOsignals during an asynchron

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 3 of 33Figure 1. Example DVB Block DiagramFigure 2. Example GPS Block DiagramThe “Reference Des

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 30 of 33Ordering InformationTable 17.Ordering InformationOrdering Code DescriptionSilicon for b

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 31 of 33PCB Layout Recommendations[16]The following recommendations should be followed to ensur

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 32 of 33© Cypress Semiconductor Corporation, 2006. The information contained herein is subject

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 33 of 33Document History Page Document Title: CY7C68033/CY7C68034 EZ-USB NX2LP-Flex™ Flexible

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 4 of 33BusesThe NX2LP-Flex features an 8- or 16-bit ‘FIFO’ bidirectionaldata bus, multiplexed o

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 5 of 33Figure 4. NX2LP-Flex Enumeration SequenceNormal Operation ModeIn Normal Operation Mode,

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 6 of 33If Autovectoring is enabled (AV2EN = 1 in the INTSET-UPregister), the NX2LP-Flex substit

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 7 of 33If Autovectoring is enabled (AV4EN = 1 in the INTSET-UPregister), the NX2LP-Flex substit

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 8 of 33Wakeup PinsThe 8051 puts itself and the rest of the chip into a power-downmode by settin

CY7C68033/CY7C68034Document #: 001-04247 Rev. *D Page 9 of 33Endpoint RAMSize• 3 × 64 bytes (Endpoints 0 and 1)• 8 × 512 bytes (Endpoints 2, 4, 6, 8