Cypress CY7C1380C Manuel d'utilisateur

18-Mb (512K x 36/1M x 18) Pipelined SRAMCY7C1380CCY7C1382CCypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-94

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 10 of 36ADSP84 A4 B9 Input-SynchronousAddress Strobe from Processor, sampled on the rising edge of

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 11 of 36VDDQ4,11,20,27,54,61,70,77A1,A7,F1,F7,J1,J7,M1,M7,U1,U7C3,C9,D3,D9,E3,E9,F3,F9,G3,G9,J3,J9

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 12 of 36Functional OverviewAll synchronous inputs pass through input registers controlledby the ri

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 13 of 36Asserting ADV LOW at clock rise will automatically incrementthe burst counter to the next

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 14 of 36READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-StateWRITE Cycle, Continue Burst

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 15 of 36IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1380C incorporates a serial boundary scan t

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 16 of 36TDI and TDO balls as shown in the Tap Controller BlockDiagram. Upon power-up, the instruct

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 17 of 36Note that since the PRELOAD part of the command is notimplemented, putting the TAP to the

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 18 of 363.3V TAP AC Test ConditionsInput pulse levels ... ...

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 19 of 36 Identification Register DefinitionsINSTRUCTION FIELDCY7C1380C(512KX36)CY7C1382C(1MX18)DES

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 2 of 3612Logic Block Diagram – CY7C1380C (512K x 36)ADDRESSREGISTERADVCLKBURSTCOUNTER ANDLOGICCLRQ

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 20 of 36119-Ball BGA Boundary Scan Order CY7C1380C (512K x 36)BIT# BALL ID BIT# BALL ID1K437 B22H4

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 21 of 36CY7C1382C (1M x 18)BIT# BALL ID BIT# BALL ID1K437 B22H438 P43M439 N44F440 R65B441 T56A442

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 22 of 36165-Ball fBGA Boundary Scan OrderCY7C1380C (512K x 36)BIT# BALL ID BIT# BALL ID1B637N62B73

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 23 of 36CY7C1382C (1M x 18)BIT# BALL ID BIT# BALL ID0B636N61B737R62A738P63B839R44A840R35B941P46A94

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 24 of 36Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tes

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 25 of 36ISB3Automatic CE Power-down Current—CMOS InputsVDD = Max, Device Deselected, or VIN ≤ 0.3V

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 26 of 36AC Test Loads and Waveforms OUTPUTR = 317ΩR = 351Ω5pFINCLUDINGJIG ANDSCOPE(a)(b)OUTPUTRL=

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 27 of 36Switching Characteristics Over the Operating Range[19, 20]Parameter Description250 MHz 225

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 28 of 36Switching WaveformsRead Cycle Timing[21]Notes: 21. On this diagram, when CE is LOW: CE1 is

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 29 of 36Write Cycle Timing[21, 22]Switching Waveforms (continued)tCYCtCLCLKADSPtADHtADSADDRESStCHO

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 3 of 36Pin Configurations AAAAA1A0NC / 72MNC / 36MVSSVDDAAAAAAAADQPBDQBDQBVDDQVSSQDQBDQBDQBDQBVSSQ

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 30 of 36Read/Write Cycle Timing[21, 23, 24]Note: 23.The data bus (Q) remains in high-Z following a

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 31 of 36Notes: 25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table f

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 32 of 36 Ordering InformationSpeed(MHz) Ordering CodePackageName Part and Package TypeOperatingRan

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 33 of 36© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 34 of 36Package Diagrams (continued)51-85115-*B119-Lead PBGA (14 x 22 x 2.4 mm) BG119[+] Feedback

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 35 of 36Package Diagrams (continued)i486 is a trademark, and Intel and Pentium are registered tra

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 36 of 36Document History PageDocument Title: CY7C1380C/CY7C1382C 18-Mb (512K x 36/1M x 18) Pipel

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 4 of 36Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNCNCDQPCDQCDQDDQCDQDAA AAADSPVDD

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 5 of 36Pin Configurations (continued)165-ball fBGACY7C1380C (512K x 36)234 5671ABCDEFGHJKLMNPRTDO

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 6 of 36CY7C1380C–Pin DefinitionsName TQFP BGA fBGA I/O DescriptionA0, A1 , A 37,36,32,33,34,35,42,

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 7 of 36ADSP84 A4 B9 Input-SynchronousAddress Strobe from Processor, sampled on the rising edge of

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 8 of 36VSSQ5,10,21,26,55,60,71,76- - I/O Ground Ground for the I/O circuitry. VDDQ4,11,20,27,54,61

CY7C1380CCY7C1382CDocument #: 38-05237 Rev. *D Page 9 of 36CY7C1382C:Pin DefinitionsName TQFP BGA fBGA I/O DescriptionA0, A1 , A 37,36,32,33,34,35,42,