Cypress CY7C1566V18 Manuel d'utilisateur télécharger pdf

72-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.5 Cycle Read Latency)

CY7C1566V18, CY7C1577V18

CY7C1568V18, CY7C1570V18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06551 Rev. *E Revised March 11, 2008

Features

■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 400 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 800 MHz) at 400 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Core V

= 1.8V ± 0.1V; IO V

DDQ

= 1.4V to V

[1]

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C1566V18 – 8M x 8

CY7C1577V18 – 8M x 9

CY7C1568V18 – 4M x 18

CY7C1570V18 – 2M x 36

Functional Description

The CY7C1566V18, CY7C1577V18, CY7C1568V18, and

CY7C1570V18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K

. Read data is driven on the rising edges

of K and K

. Each address location is associated with two 8-bit

words (CY7C1566V18), 9-bit words (CY7C1577V18), 18-bit

words (CY7C1568V18), or 36-bit words (CY7C1570V18) that

burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ

, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the K or K

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 400 375 333 300 MHz

Maximum Operating Current x8 1400 1300 1200 1100 mA

x9 1400 1300 1200 1100

x18 1400 1300 1200 1100

x36 1400 1300 1200 1100

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

[+] Feedback [+] Feedback

1 2 3 4 5 6 ... 27 28

Résumé du contenu

Page 1 - CY7C1568V18, CY7C1570V18

72-Mbit DDR-II+ SRAM 2-Word BurstArchitecture (2.5 Cycle Read Latency)CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Cypress Semiconductor Corporatio

Page 2

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 10 of 28Truth TableThe truth table for CY7C1566V18, CY7C1577V1

Page 3

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 11 of 28Write Cycle DescriptionsThe write cycle description ta

Page 4

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 12 of 28IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs inc

Page 5

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 13 of 28IDCODEThe IDCODE instruction loads a vendor-specific,

Page 6

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 14 of 28TAP Controller State DiagramThe state diagram for the

Page 7

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 15 of 28TAP Controller Block DiagramTAP Electrical Characteris

Page 8

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 16 of 28TAP AC Switching Characteristics Over the Operating Ra

Page 9

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 17 of 28Identification Register Definitions Instruction FieldV

Page 10

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 18 of 28Boundary Scan OrderBit Number Bump ID Bit Number Bump

Page 11

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 19 of 28Power Up Sequence in DDR-II+ SRAMDDR-II+ SRAMs must be

Page 12

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 2 of 28Logic Block Diagram (CY7C1566V18)Logic Block Diagram (C

Page 13

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 20 of 28Maximum RatingsExceeding maximum ratings may impair th

Page 14

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 21 of 28ISB1Automatic Power down CurrentMax VDD, Both Ports De

Page 15

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 22 of 28AC Test Loads and WaveformsFigure 4. AC Test Loads an

Page 16 - ALL INPUT PULSES

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 23 of 28Switching Characteristics Over the Operating Range[21,

Page 17

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 24 of 28Switching WaveformsRead/Write/Deselect Sequence [29, 3

Page 18

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 25 of 28Ordering Information Not all of the speed, package, an

Page 19 - Power Up Waveforms

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 26 of 28333 CY7C1566V18-333BZC 51-85195 165-Ball Fine Pitch Ba

Page 20

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 27 of 28Package DiagramFigure 6. 165-Ball FBGA (15 x 17 x 1.4

Page 21

Document Number: 001-06551 Rev. *E Revised March 11, 2008 Page 28 of 28QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by

Page 22 - AC Test Loads and Waveforms

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 3 of 28Logic Block Diagram (CY7C1568V18)Logic Block Diagram (C

Page 23

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 4 of 28Pin Configuration The pin configuration for CY7C1566V18

Page 24 - Switching Waveforms

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 5 of 28CY7C1568V18 (4M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ AAR/WB

Page 25

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 6 of 28Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]Input

Page 26

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 7 of 28ZQ Input Output Impedance Matching Input. This input is

Page 27 - Package Diagram

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 8 of 28Functional OverviewThe CY7C1566V18, CY7C1577V18, CY7C15

Page 28 - Document History Page

CY7C1566V18, CY7C1577V18CY7C1568V18, CY7C1570V18Document Number: 001-06551 Rev. *E Page 9 of 28Echo ClocksEcho clocks are provided on the DDR-II+ to s

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