Cypress AutoStore STK17TA8 Manuel d'utilisateur télécharger pdf (Page 7)

STK17TA8

Document #: 001-52039 Rev. ** Page 7 of 23

SRAM WRITE Cycles #1 and #2

Figure 7. SRAM WRITE Cycle #1: W Controlled

[7, 8]

Figure 8. SRAM WRITE Cycle #2: E Controlled

[7, 8]

Notes

7. If W

is low when E goes low, the outputs remain in the high-impedance state.

E or W must be ≥ V

during address transitions.

NO.

Symbols

Parameter

STK17TA8-25 STK17TA8-45

Units

#1 #2 Alt. Min Max Min Max

11 t

AVAV

Write Cycle Time 25 45 ns

13 t

WLWH

WLEH

Write Pulse Width 20 30 ns

14 t

ELWH

ELEH

Chip Enable to End of Write 20 30 ns

15 t

DVWH

DVEH

Data Set-up to End of Write 10 15 ns

16 t

WHDX

EHDX

Data Hold after End of Write 0 0 ns

17 t

AVWH

AVEH

Address Set-up to End of Write 20 30 ns

18 t

AVWL

AVEL

Address Set-up to Start of Write 0 0 ns

19 t

WHAX

EHAX

Address Hold after End of Write 0 0 ns

20 t

WLQZ

5, 7

Write Enable to Output Disable 10 15 ns

21 t

WHQX

Output Active after End of Write 3 3 ns

PREVIOUS DATA

DATA OUT

ADDRESS

AVAV

WHDX

DATA IN

WHAX

WLWH

AVWL

AVWH

DATA VALID

WLQZ

DVWH

HIGH IMPEDANCE

WHQX

ELWH

DATA IN

AVAV

EHDX

WLEH

EHAX

AVEL

AVEH

DATA VALID

DVEH

HIGH IMPEDANCE

ELEH

DATA OUT

ADDRESS

DATA IN

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Cypress AutoStore STK17TA8 Manuel d'utilisateur Page 7

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