Cypress CY7C1312BV18 Manuel d'utilisateur télécharger pdf (Page 3)

CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Document #: 38-05619 Rev. *F Page 3 of 29

Logic Block Diagram (CY7C1312BV18)

Logic Block Diagram (CY7C1314BV18)

512K x 18 Array

CLK

(18:0)

Gen.

Control

Logic

Address

[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Reg.

BWS

[1:0]

REF

Write Add. Decode

Write

Reg

(18:0)

DOFF

[17:0]

Write

Reg

512K x 18 Array

256K x 36 Array

CLK

(17:0)

Gen.

Control

Logic

Address

[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Reg.

BWS

[3:0]

REF

Write Add. Decode

Write

Reg

(17:0)

DOFF

[35:0]

Write

Reg

256K x 36 Array

[+] Feedback

1 2 3 4 5 6 7 8 ... 28 29

18-Mbit QDR™-II SRAM 2-Word 1
Burst Architecture 1
CY7C1310BV18, CY7C1910BV18 10
CY7C1312BV18, CY7C1314BV18 10
[+] Feedback 16
Power Up Sequence 19
DLL Constraints 19
Operating Range 20
Thermal Resistance 22
Capacitance 22
Package Diagram 27
Document History Page 29

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Cypress CY7C1312BV18 Manuel d'utilisateur Page 3

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