Cypress CY7C1250V18 Manuel d'utilisateur télécharger pdf (Page 23)

CY7C1246V18, CY7C1257V18

CY7C1248V18, CY7C1250V18

Document Number: 001-06348 Rev. *D Page 23 of 27

Switching Waveforms

Read/Write/Deselect Sequence

[28, 29, 30]

Figure 5. Waveform for 2.0 Cycle Read Latency

DON’T CARE UNDEFINED

READ

READ NOP WRITE

WRITE

NOP

R/W

CYC

QVLD

NOP

QVLD

CCQO

CQOH

QVLD

NOP

KHKH

(Read Latency = 2.0 Cycles)

NOP

CCQO

CLZ

CHZ

D20

D21

D30

D31

CQDOH

Q00

Q11

Q01

Q10

DOH

Q40

Q41

CQD

CQH

CQHCQH

Notes

28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

29. Outputs are disabled (High-Z) one clock cycle after a NOP.

30. The third NOP cycle between read to write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency

operation, it may be required to avoid bus contention.

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Cypress CY7C1250V18 Manuel d'utilisateur Page 23

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