Cypress DCT-1D Guide de l'utilisateur télécharger pdf (Page 34)

CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUS

7 0 07152331

9000_0000

sel[0]sel[1]sel[2]sel[3]

a) b)

tx_empty rx_full

rx_fulltx_empty

rx/tx rx/tx

Figure 3.5: a) Address map for the UART connected to an 8 bit bus b) Address map

for the UART connected to a 32 bit bus. The sel-signals are used to address individual

bytes.

deﬁnition of the wishbone SystemVerilog interface can be found in the appendix sec-

tion B.5.

Listing 3.1: Lab skeleton lab1_uart_top.sv.

module l a b 1 _ u a r t _ t o p

( wishbone . s l a v e wb ,

outpu t wi r e i n t _ o ,

i n pu t wire s r x _ p a d _ i ,

outpu t wi r e s t x _ p a d _ o ) ;

a s s i g n i n t _ o = 1 ’ b0 ; / / I n t e r r u p t , n o t u s e d i n t h i s l a b

a s s i g n wb . e r r = 1 ’ b0 ; / / Er r or , n o t u s ed i n t h i s l a b

a s s i g n wb . r t y = 1 ’ b0 ; / / R e t r y , n o t u s e d i n t h i s l a b

a s s i g n wb . ack = wb . s t b ; / / c h ange i f ne e ded

/ / Here you m ust i n s t a n t i a t e l a b 0 _ u a r t or c u t and p a s t e

/ / You w i l l a l s o h a v e t o c h ang e t h e i n t e r f a c e o f l a b 0 _ u a r t t o make t h i s work .

a s s i g n s t x _ p a d _ o = s r x _ p a d _ i ; / / Change t h i s l i n e . . : )

endmodule

Preparation task 3

Write Verilog code for the Wishbone interface of your UART.

Preparation task 4

Inspect the driver routines

getch

and

putch

in the ﬁle

monitor/firmware/src/uartfun.c

. You will also have to look in

uartfun.h

3.3.3 The Monitor

The monitor directory contains a couple of Verilog ﬁles that implements an 8 kB

block RAM at base address 0x4001_0000. This RAM will contain the stack of the

monitor. The monitor itself is implemented in a 24 kB block ROM at base address

0x4000_0000. The contents of the block ROM is in the Verilog ﬁle mon_prog_bram_contents.v.

The software is in the sub directories firmware/src and firmware/include.

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