Cypress CY14B256L Manuel d'utilisateur

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CY14B256L
256 Kbit (32K x 8) nvSRAM
Cypress Semiconductor Corporation 198 Champion Court San Jose
,
CA 95134-1709 408-943-2600
Document Number: 001-06422 Rev. *H Revised January 30, 2009
Features
25 ns, 35 ns, and 45 ns access times
Pin compatible with STK14D88
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
RECALL to SRAM initiated by software or power up
Unlimited READ, WRITE, and RECALL cycles
200,000 STORE cycles to QuantumTrap
20 year data retention at 55°C
Single 3V +20%, –10% operation
Commercial and industrial temperature
32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages
RoHS compliance
Functional Description
The Cypress CY14B256L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB
pin.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
Quantum Trap
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
13
-
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
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Résumé du contenu

Page 1 - 256 Kbit (32K x 8) nvSRAM

CY14B256L256 Kbit (32K x 8) nvSRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600Document Number: 001-0

Page 2

CY14B256LDocument Number: 001-06422 Rev. *H Page 10 of 18SRAM Write CycleParameterDescription25 ns 35 ns 45 ns UnitMin Max Min Max Min MaxCypressPar

Page 3

CY14B256LDocument Number: 001-06422 Rev. *H Page 11 of 18AutoStore or Power Up RECALLParameter Alt DescriptionCY14B256LUnitMin MaxtHRECALL [12]tRESTOR

Page 4

CY14B256LDocument Number: 001-06422 Rev. *H Page 12 of 18Software Controlled STORE/RECALL CycleThe software controlled STORE/RECALL cycle follows. [15

Page 5

CY14B256LDocument Number: 001-06422 Rev. *H Page 13 of 18Hardware STORE CycleParameter Alt DescriptionCY14B256LUnitMin MaxtPHSBtHLHXHardware STORE Pul

Page 6

CY14B256LDocument Number: 001-06422 Rev. *H Page 14 of 18Ordering InformationSpeed(ns)Ordering Code Package Diagram Package TypeOperatingRange25 CY14B

Page 7

CY14B256LDocument Number: 001-06422 Rev. *H Page 15 of 1845 CY14B256L-SZ45XCT 51-85127 32-pin SOIC CommercialCY14B256L-SZ45XC 51-85127 32-pin SOIC CY

Page 8

CY14B256LDocument Number: 001-06422 Rev. *H Page 16 of 18Figure 15. 48-Pin (300 mil) Shrunk Small Outline Package (51-85061)Package Diagrams (continu

Page 9

CY14B256LDocument Number: 001-06422 Rev. *H Page 17 of 18Document History PageDocument Title: CY14B256L 256 Kbit (32K x 8) nvSRAM Document Number: 001

Page 10 - CY14B256L

Document Number: 001-06422 Rev. *H Revised January 30, 2009 Page 18 of 18AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor

Page 11 - HRECALL

CY14B256LDocument Number: 001-06422 Rev. *H Page 2 of 18Pin ConfigurationsFigure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOPPin DefinitionsPin Name

Page 12

CY14B256LDocument Number: 001-06422 Rev. *H Page 3 of 18Device OperationThe CY14B256L nvSRAM is made up of two functional compo-nents paired in the sa

Page 13

CY14B256LDocument Number: 001-06422 Rev. *H Page 4 of 18once again exceeds the sense voltage of VSWITCH, a RECALLcycle is automatically initiated and

Page 14

CY14B256LDocument Number: 001-06422 Rev. *H Page 5 of 18Preventing StoreDisable the AutoStore function by initiating an AutoStore Disablesequence. A s

Page 15

CY14B256LDocument Number: 001-06422 Rev. *H Page 6 of 18Table 1. Hardware Mode Selection CE WE OEA14 – A0Mode IO PowerH X X X Not Selected Output Hig

Page 16

CY14B256LDocument Number: 001-06422 Rev. *H Page 7 of 18Maximum RatingsExceeding maximum ratings may shorten the useful life of thedevice. These user

Page 17

CY14B256LDocument Number: 001-06422 Rev. *H Page 8 of 18CapacitanceIn the following table, the capacitance parameters are listed.[5]Parameter Descript

Page 18 - PSoC Solutions

CY14B256LDocument Number: 001-06422 Rev. *H Page 9 of 18AC Switching Characteristics SRAM Read CycleParameterDescription25 ns 35 ns 45 ns UnitMin Ma

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