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PRELIMINARY

2-Mbit (64K x 32) Flow-Through Sync SRAM

CY7C1336H

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-00210 Rev. *A Revised February 6, 2006

Features

• 64K x 32 common I/O

• 3.3V core power supply

• 3.3V I/O supply

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 8.0 ns (100-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Supports 3.3V I/O level

• Offered in JEDEC-standard lead-free 100-pin TQFP

package

• “ZZ” Sleep Mode option

Functional Description

[1]

The CY7C1336H is a 64K x 32 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and

), Burst

Control inputs (ADSC

, ADSP,

and

ADV), Write Enables

(BW

[A:D]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1336H allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP

) or the cache Controller

Address Strobe (ADSC

) inputs. Address advancement is

controlled by the Address Advancement (ADV) input.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC

) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV

The CY7C1336H operates from a +3.3V core power supply

while all outputs may operate with a +3.3V supply. All inputs

and outputs are JEDEC-standard JESD8-5-compatible.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

ADDRESS

BURST

COUNTER

AND LOGIC

CLR

ENABLE

SENSE

AMPS

OUTPUT

BUFFERS

INPUT

REGISTERS

MEMORY

ARRAY

MODE

[1:0]

0, A1, A

ADV

CLK

ADSP

ADSC

BWE

CE1

CE2

CE3

SLEEP

CONTROL

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

agram

[+] Feedback

1 2 3 4 5 6 ... 14 15

PRELIMINARY 1
CY7C1336H 1

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Page 1 - CY7C1336H

PRELIMINARY2-Mbit (64K x 32) Flow-Through Sync SRAMCY7C1336HCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943

Page 2

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 10 of 15Timing Diagrams Read Cycle Timing[16]Note: 16. On this diagram, when CE is LOW, CE1 is

Page 3

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 11 of 15Write Cycle Timing[16, 17]Note: 17.Full width Write can be initiated by either GW LOW;

Page 4

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 12 of 15Read/Write Timing[16, 18, 19]Notes: 18. The data bus (Q) remains in High-Z following a

Page 5

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 13 of 15ZZ Mode Timing[20, 21] Notes: 20. Device must be deselected when entering ZZ mode. See

Page 6

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 14 of 15© Cypress Semiconductor Corporation, 2006. The information contained herein is subject

Page 7

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 15 of 15Document History PageDocument Title: CY7C1336H 2-Mbit (64K x 32) Flow-Through Sync SRAM

Page 8

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 2 of 15Selection Guide133 MHz 100 MHz UnitMaximum Access Time 6.5 8.0 nsMaximum Operating Curr

Page 9

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 3 of 15Pin DefinitionsName I/O DescriptionA0, A1, AInput-SynchronousAddress Inputs used to sele

Page 10

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 4 of 15Functional OverviewAll synchronous inputs pass through input registers controlledby the

Page 11

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 5 of 15ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min. Max. UnitID

Page 12

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 6 of 15Truth Table for Read/Write[2, 3]Function GW BWE BWDBWCBWBBWARead HHXXXXRead HLHHHHWrite

Page 13

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 7 of 15Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not t

Page 14

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 8 of 15Capacitance[9]Parameter Description Test Conditions100 TQFPMax. UnitCINInput Capacitance

Page 15

PRELIMINARYCY7C1336HDocument #: 001-00210 Rev. *A Page 9 of 15 Switching Characteristics Over the Operating Range[10, 11] Parameter Description133 MHz

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