Cypress CY7C1387FV25 Manuel d'utilisateur
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18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05548 Rev. *E Revised Feburary 15, 2007
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
• Depth expansion without wait state
•2.5V +
5% power supply (V
DD
)
• Fast clock-to-output times, 2.6 ns (for 250 MHz device)
• Provides high-performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed writes
• Asynchronous output enable
• CY7C1386DV25/CY7C1387DV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1386FV25/CY7C1387FV25 available in Pb-free and
non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
Functional Description
[1]
The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive edge triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE
1
), depth expansion chip enables (CE
2
and
CE
3
[2]
), burst control inputs (ADSC, ADSP, and ADV), write
enables (BW
X
, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE
) and the
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP
) or
address strobe controller (ADSC
) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see Pin Definitions on page 6 and Truth Table
[4,
5, 6, 7, 8, 9]
on page 9 for further details). Write cycles can be
one to four bytes wide as controlled by the byte write control
inputs. GW
active
LOW
causes all bytes to be written.
This
device incorporates an additional pipelined enable register
which delays turning off the output buffers an additional cycle
when a deselect is executed.This feature allows depth
expansion without penalizing system performance.
The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 operates from a +2.5V power supply. All
inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 2.6 3.0 3.4 ns
Maximum Operating Current 350 300 275 mA
Maximum CMOS Standby Current 70 70 70 mA
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE
3,
CE
2
are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
[+] Feedback
Résumé du contenu
Page 1 - CY7C1387DV25, CY7C1387FV25
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAMCY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Cypress Semiconductor Corporation • 198 Champi
Page 2 - (1M x 18)
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 10 of 30Partial Truth Table for Read/Write [5, 10]Function
Page 3 - Pin Configurations
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 11 of 30IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1386
Page 4 - CY7C1386FV25 (512K x 36)
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 12 of 30Instruction RegisterThree-bit instructions can be s
Page 5 - CY7C1386DV25 (512K x 36)
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 13 of 30The shifting of data for the SAMPLE and PRELOAD pha
Page 6
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 14 of 30TAP AC Test ConditionsInput pulse levels ...
Page 7
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 15 of 30Identification Register DefinitionsInstruction Fiel
Page 8
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 16 of 30119-Ball BGA Boundary Scan Order[14, 15] Bit # Ball
Page 9
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 17 of 30165-Ball BGA Boundary Scan Order[14, 16]Bit # Ball
Page 10
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 18 of 30Maximum RatingsExceeding the maximum ratings may im
Page 11
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 19 of 30Capacitance [19]Parameter Description Test Conditio
Page 12
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 2 of 30Logic Block Diagram – CY7C1386DV25/CY7C1386FV25 [3]
Page 13
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 20 of 30Switching Characteristics Over the Operating Range
Page 14
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 21 of 30Switching Waveforms Read Cycle Timing [26]tCYCtCLCL
Page 15
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 22 of 30Write Cycle Timing [26, 27]Switching Waveforms (co
Page 16
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 23 of 30Read/Write Cycle Timing [26, 28, 29]Switching Wavef
Page 17
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 24 of 30ZZ Mode Timing [30, 31]Switching Waveforms (contin
Page 18
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 25 of 30Ordering InformationNot all of the speed, package,
Page 19
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 26 of 30250 CY7C1386DV25-250AXC 51-85050 100-pin Thin Quad
Page 20
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 27 of 30Package Diagrams Figure 1. 100-Pin Plastic Quad Fla
Page 21
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 28 of 30Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115
Page 22
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 29 of 30© Cypress Semiconductor Corporation, 2006-2007. The
Page 23
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 3 of 30Pin Configurations AAAAA1A0NC/72MNC/36MVSSVDDAAAAAAA
Page 24
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 30 of 30Document History PageDocument Title: CY7C1386DV25/C
Page 25
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 4 of 30Pin Configurations (continued)2345671ABCDEFGHJKLMNP
Page 26
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 5 of 30Pin Configurations (continued)165-Ball FBGA Pinout
Page 27
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 6 of 30Pin DefinitionsName IO DescriptionA0, A1, A Input-Sy
Page 28
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 7 of 30Functional OverviewAll synchronous inputs pass throu
Page 29
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 8 of 30The write signals (GW, BWE, and BWX) and ADV inputs
Page 30
CY7C1386DV25, CY7C1386FV25CY7C1387DV25, CY7C1387FV25Document Number: 38-05548 Rev. *E Page 9 of 30ZZ Mode Electrical CharacteristicsParameter Descript
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