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CY7C1217H

1-Mbit (32K x 36) Flow-Through Sync SRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05670 Rev. *B Revised July 6, 2006

Features

• 32K x 36 common I/O

• 3.3V core power supply (V

)

• 2.5V/3.3V I/O power supply (V

DDQ

)

• Fast clock-to-output times

— 6.5 ns (for 133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• “ZZ” Sleep Mode option

Functional Description

[1]

The CY7C1217H is a 32K x 36 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and CE

), Burst

Control inputs (ADSC

, ADSP, and ADV), Write Enables

(BW

[A:D]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE

) and the ZZ pin.

The CY7C1217H allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP

) or the cache Controller

Address Strobe (ADSC

) inputs. Address advancement is

controlled by the Address Advancement (ADV

) input.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP

) or

Address Strobe Controller (ADSC

) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1217H operates from a +3.3V core power supply

while all outputs may operate either with a +2.5V or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.0 ns

Maximum Operating Current 225 205 mA

Maximum Standby Current 40 40 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

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Page 1 - CY7C1217H

CY7C1217H1-Mbit (32K x 36) Flow-Through Sync SRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Docume

Page 2

CY7C1217HDocument #: 38-05670 Rev. *B Page 10 of 16Switching Characteristics Over the Operating Range [10, 11]Parameter Description133 MHz 100 MHzUnit

Page 3

CY7C1217HDocument #: 38-05670 Rev. *B Page 11 of 16Timing Diagrams Read Cycle Timing[16]Note: 16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is

Page 4

CY7C1217HDocument #: 38-05670 Rev. *B Page 12 of 16Write Cycle Timing[16, 17]Note: 17.Full width Write can be initiated by either GW LOW; or by GW HIG

Page 5

CY7C1217HDocument #: 38-05670 Rev. *B Page 13 of 16Read/Write Timing[16, 18, 19] Notes: 18. The data bus (Q) remains in High-Z following a Write cycle

Page 6

CY7C1217HDocument #: 38-05670 Rev. *B Page 14 of 16ZZ Mode Timing[20, 21]Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descrip

Page 7

CY7C1217HDocument #: 38-05670 Rev. *B Page 15 of 16© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change w

Page 8

CY7C1217HDocument #: 38-05670 Rev. *B Page 16 of 16Document History PageDocument Title: CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAMDocument Num

Page 9

CY7C1217HDocument #: 38-05670 Rev. *B Page 2 of 16Logic Block DiagramADDRESSREGISTERBURSTCOUNTERAND LOGICCLRQ1Q0ENABLEREGISTERSENSEAMPSOUTPUTBUFFERSIN

Page 10

CY7C1217HDocument #: 38-05670 Rev. *B Page 3 of 16Pin Configuration 100-Pin TQFP AAAAA1A0NC/72MNC/36MVSSVDDNC/9MAAAAANC/4MDQPBDQBVDDQVSSQDQBDQBDQBDQBV

Page 11

CY7C1217HDocument #: 38-05670 Rev. *B Page 4 of 16Pin Descriptions Name I/O DescriptionA0, A1, A Input-SynchronousAddress Inputs used to select one of

Page 12

CY7C1217HDocument #: 38-05670 Rev. *B Page 5 of 16Functional OverviewAll synchronous inputs pass through input registers controlledby the rising edge

Page 13

CY7C1217HDocument #: 38-05670 Rev. *B Page 6 of 16ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min. Max. UnitIDDZZSleep mod

Page 14

CY7C1217HDocument #: 38-05670 Rev. *B Page 7 of 16Truth Table for Read/Write[2, 3]Function GW BWE BWDBWCBWBBWARead HHXXXXRead HLHHHHWrite Byte (A, DQP

Page 15

CY7C1217HDocument #: 38-05670 Rev. *B Page 8 of 16Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Stora

Page 16

CY7C1217HDocument #: 38-05670 Rev. *B Page 9 of 16 Capacitance[9]Parameter Description Test Conditions100 TQFP Max. UnitCINInput Capacitance TA = 2

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