Cypress Perform CY7C136A Manuel d'utilisateur télécharger pdf

2K x 8 Dual-Port Static RAM

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-06031 Rev. *E Revised March 24, 2009

Features

■ True dual-ported memory cells that enable simultaneous reads

of the same memory location

■ 2K x 8 organization

■ 0.65 micron CMOS for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: I

= 110 mA (maximum)

■ Fully asynchronous operation

■ Automatic power down

■ Master CY7C132/CY7C136/CY7C136A

[1]

easily expands data

bus width to 16 or more bits using slave CY7C142/CY7C146

■ BUSY output flag on CY7C132/CY7C136/CY7C136A;

BUSY input on CY7C142/CY7C146

■ INT flag for port to port communication (52-Pin PLCC/PQFP

versions)

■ CY7C136, CY7C136A, and CY7C146 available in 52-pin

PLCC and 52-pin PQFP packages

■ Pb-free packages available

Functional Description

The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146

are high speed CMOS 2K x 8 dual-port static RAMs. Two ports

are provided to permit independent access to any location in

memory. The CY7C132, CY7C136, and CY7C136A can be used

as either a standalone 8-bit dual-port static RAM or as a

MASTER dual-port RAM, in conjunction with the

CY7C142/CY7C146 SLAVE dual-port device. They are used in

systems that require 16-bit or greater word widths. This is the

solution to applications that require shared or buffered data, such

as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port has independent control pins; chip enable (CE

), write

enable (R/W

), and output enable (OE). BUSY flags are provided

on each port. In addition, an interrupt flag (INT

) is provided on

each port of the 52-pin PLCC version. BUSY

signals that the port

is trying to access the same location currently being accessed

by the other port. On the PLCC version, INT

is an interrupt flag

indicating that data is placed in an unique location (7FF for the

left port and 7FE for the right port).

An automatic power down feature is controlled independently on

each port by the chip enable (CE

) pins.

R/W

BUSY

10L

10R

R/W

I/O

BUSY

INT

ARBITRATION

LOGIC

(7C132/7C136 ONLY)

AND

INTERRUPTLOGIC

(7C136/7C146ONLY)

CONTROL

I/O

CONTROL

I/O

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

[2]

[3]

[2]

Logic Block Diagram

Notes

1. CY7C136 and CY7C136A are functionally identical.

2. CY7C132/CY7C136/CY7C136A (Master): BUSY

is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input.

3. Open drain outputs; pull up resistor required.

[+] Feedback

1 2 3 4 5 6 ... 14 15

Résumé du contenu

Page 1 - 2K x 8 Dual-Port Static RAM

2K x 8 Dual-Port Static RAMCY7C132, CY7C136CY7C136A, CY7C142, CY7C146Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709

Page 2

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 10 of 15Figure 10. Busy Timing Diagram No. 2 (Address Arbitration)Figure

Page 3

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 11 of 15Interrupt Timing Diagrams [16]Figure 12. Left Side Sets INTRFigur

Page 4

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 12 of 15Figure 16. Typical DC and AC Characteristics1.41.00.44.0 4.5 5.0

Page 5

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 13 of 15Ordering Information Speed(ns)Ordering CodePackage DiagramPackage

Page 6

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 14 of 15Package DiagramsFigure 17. 52-Pin Plastic Leaded Chip Carrier, 51

Page 7

Document #: 38-06031 Rev. *E Revised March 24, 2009 Page 15 of 15All products and company names mentioned in this document may be the trademarks of th

Page 8

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 2 of 15PinoutsFigure 1. 52-Pin PLCC (Top View) Figure 2. 52-Pin PQFP (To

Page 9

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 3 of 15Maximum RatingsExceeding maximum ratings may impair the useful life

Page 10 - CY7C136A, CY7C142, CY7C146

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 4 of 15 CapacitanceThis parameter is guaranteed but not tested.Parameter D

Page 11 - Interrupt Timing Diagrams

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 5 of 15Write Cycle[12]tWCWrite Cycle Time 15 25 30 nstSCECE LOW to Write E

Page 12 - [+] Feedback

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 6 of 15Switching Characteristics Over the Operating Range (Speeds -35, -45

Page 13

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 7 of 15Interrupt Timing [16]tWINSR/W to INTERRUPT Set Time 25 35 45 nstEIN

Page 14

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 8 of 15Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7

Page 15

CY7C132, CY7C136CY7C136A, CY7C142, CY7C146Document #: 38-06031 Rev. *E Page 9 of 15Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Por

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