search

Cypress CY7C1353G Manuel d'utilisateur

Naviguer en ligne ou télécharger Manuel d'utilisateur pour Moniteurs Cypress CY7C1353G. Cypress CY7C1353G User Manual Manuel d'utilisatio

  • Télécharger
  • Ajouter à mon manuel
  • Imprimer
  • Page
    / 13
  • Table des matières
  • MARQUE LIVRES
    • Noté. / 5. Basé sur avis des utilisateurs
Vue de la page 0
4-Mbit (256K x 18) Flow-through SRAM
wi
t
h N
o
BL™ Ar
c
hi
tectu
r
e
CY7C1353G
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05515 Rev. *E Revised July 09, 2007
Features
• Supports up to 133-MHz bus operations with zero wait
states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the
need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 256K x 18 common IO architecture
• 2.5V/3.3V IO power supply (V
DDQ
)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self timed writes
• Asynchronous Output Enable
• Available in Pb-free 100-Pin TQFP package
• Burst Capability — linear or interleaved burst order
• Low standby power
Functional Description
[1]
The CY7C1353G is a 3.3V, 256K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN
) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
[A:B]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE
) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Note:
1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
C
MODE
BW
A
BW
B
WE
CE
1
CE
2
CE
3
OE
READ LOGIC
DQs
DQP
A
DQP
B
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
ZZ
SLEEP
CONTROL
Logic Block Diagram
[+] Feedback
Vue de la page 0
1 2 3 4 5 6 ... 12 13

Résumé du contenu

Page 1

4-Mbit (256K x 18) Flow-through SRAMwith NoBL™ ArchitectureCY7C1353GCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 •

Page 2

CY7C1353GDocument #: 38-05515 Rev. *E Page 10 of 13Switching WaveformsRead/Write Waveforms[19, 20, 21]Notes: 19.For this waveform ZZ is tied low.20.Wh

Page 3

CY7C1353GDocument #: 38-05515 Rev. *E Page 11 of 13NOP, STALL and DESELECT Cycles[19, 20, 22]ZZ Mode Timing[23,24]Notes: 22.The IGNORE CLOCK EDGE or S

Page 4

CY7C1353GDocument #: 38-05515 Rev. *E Page 12 of 13© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to cha

Page 5 - [+] Feedback

CY7C1353GDocument #: 38-05515 Rev. *E Page 13 of 13Document History PageDocument Title: CY7C1353G 4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Arch

Page 6

CY7C1353GDocument #: 38-05515 Rev. *E Page 2 of 13Selection Guide133 MHz 100 MHz UnitMaximum Access Time 6.5 8.0 nsMaximum Operating Current 225 205

Page 7 - Operating Range

CY7C1353GDocument #: 38-05515 Rev. *E Page 3 of 13Pin Definitions Name IO DescriptionA0, A1, A Input-SynchronousAddress Inputs used to select one of t

Page 8 - AC Test Loads and Waveforms

CY7C1353GDocument #: 38-05515 Rev. *E Page 4 of 13Functional OverviewThe CY7C1353G is a synchronous flow-through burst SRAMdesigned specifically to el

Page 9

CY7C1353GDocument #: 38-05515 Rev. *E Page 5 of 13 Linear Burst Address Table (MODE = GND)First AddressA1, A0SecondAddressA1, A0Third AddressA1, A0Fo

Page 10 - Switching Waveforms

CY7C1353GDocument #: 38-05515 Rev. *E Page 6 of 13Partial Truth Table for Read/Write[2, 3, 9]Function WE BWABWBRead HXXWrite – No bytes written L H HW

Page 11 - ZZ Mode Timing

CY7C1353GDocument #: 38-05515 Rev. *E Page 7 of 13Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These user guideli

Page 12 - CY7C1353G

CY7C1353GDocument #: 38-05515 Rev. *E Page 8 of 13 .Capacitance[12]Parameter Description Test Conditions100 TQFPMax UnitCINInput Capacitance TA = 25°C

Page 13

CY7C1353GDocument #: 38-05515 Rev. *E Page 9 of 13Switching Characteristics Over the Operating Range[17, 18]Parameter Description–133 –100 UnitMin Max

Commentaires sur ces manuels

Pas de commentaire
Produits connexes et manuels pour Moniteurs Cypress CY7C1353G
Moniteurs Cypress CY7C1298H Manuel d'utilisateur   (16 pages)
  • Condor HealthRider Firesense Vir2 Elecard
  • Broan Non Apple Smartphones Gateway Lecteurs MP3/MP4 SIIG Interface de câble/adaptateurs de genre Beurer Outils de mesure et de mise en page
  • Philips DS3100 Bosch SMZPC002UC HP TFT7210R Electrolux EW30IC60LB
  • Panasonic PTAE700E Instructions d'exploitation Virtu USA VST-2011-BAS Guide d'installation Samsung BD-J5500 Manuel de l'utilisateur Zanussi TA522 Manuel de l'utilisateur ASROCK Z87 Pro3 Manuel de l'utilisateur