Cypress CY7C68320C Manuel d'utilisateur

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EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge
CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document 001-05809 Rev. *A Revised November 30, 2006
Features
Fixed-function mass storage device—requires no firmware
Two power modes: Self-powered and USB bus-powered to
enable bus powered CF readers and truly portable USB
hard drives
Certified compliant for USB 2.0 (TID# 40490119), the USB
Mass Storage Class, and the USB Mass Storage Class
Bulk-Only Transport (BOT) Specification
Operates at high-speed (480 Mbps) or full-speed (12 Mbps)
USB
Complies with ATA/ATAPI-6 specification
Supports 48 bit addressing for large hard drives
Supports ATA security features
Supports any ATA command with the ATACB function
Supports mode page 5 for BIOS boot support
Supports ATAPI serial number VPD page retrieval for Digital
Rights Management (DRM) compatibility
Supports PIO modes 0, 3, and 4, multiword DMA mode 2,
and UDMA modes 2, 3, and 4
Uses one small external serial EEPROM for storage of USB
descriptors and device configuration data
ATA interface IRQ signal support
Supports one or two ATA/ATAPI devices
Supports CompactFlash and one ATA/ATAPI device
Supports board-level manufacturing test using the USB I/F
Can place the ATA interface in high impedance (Hi-Z) to
allow sharing of the ATA bus with another controller (i.e., an
IEEE-1394 to ATA bridge chip or MP3 Decoder)
Low-power 3.3V operation
Fully compatible with native USB mass storage class drivers
Cypress mass storage class drivers available for Windows
(98SE, ME, 2000, XP) and Mac OS X operating systems
Features (CY7C68320C/CY7C68321C only)
Supports HID interface or custom GPIOs to enable features
such as single button backup, power-off, LED-based notifi-
cation, etc.
56-pin QFN and 100-pin TQFP lead-free packages
CY7C68321C is ideal for battery-powered designs
CY7C68320C is ideal for self- and bus-powered designs
Features (CY7C68300C/CY7C68301C only)
Pin-compatible with CY7C68300A (using Backward
Compatibility mode)
56-pin SSOP and 56-pin QFN lead-free packages
CY7C68301C is ideal for battery-powered designs
CY7C68300C is ideal for self- and bus-powered designs
USB 2.0
Tranceiver
CY Smart USB
FS/HS Engine
4 kByte FIFO
PLL
I
2
C Bus Master
ATA
Interface
Logic
Data
Control
24
MHz
XTAL
16 Bit ATA DataUSB
D+
D-
Internal Control Logic
VBUS
ATA Interface
Control Signals
Misc control signals and GPIO
SDA
SCL
ATA 3-state Control
Reset
Block Diagram
[+] Feedback
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Résumé du contenu

Page 1 - CY7C68320C/CY7C68321C

EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI BridgeCY7C68300C/CY7C68301CCY7C68320C/CY7C68321CCypress Semiconductor Corporation • 198 Champion Court • San Jose,

Page 2

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 10 of 4268 34 41 DA0 O/Z[1]Driven HIGH after 2 ms delayATA address.69 35 42

Page 3 - CY7C68301C

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 11 of 42Additional Pin DescriptionsThe following sections provide additional

Page 4 - 56-pin QFN

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 12 of 42SYSIRQThe SYSIRQ pin provides a way for systems to request servicefr

Page 5 - CY7C68321C

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 13 of 42Figure 8. SYSIRQ Latching AlgorithmDRVPWRVLDWhen this pin is enable

Page 6

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 14 of 42interface and the attached mass storage device, especially ifUltra D

Page 7 - 100-pin TQFP

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 15 of 42HID Functions for Button ControlsCypress’s CY7C68320C/CY7C68321C has

Page 8

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 16 of 42 Table 6. ATACB Field DescriptionsByte Field Name Field Description0

Page 9

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 17 of 423 bmATACBRegisterSelect This field controls which of the taskfile re

Page 10

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 18 of 42Operating Modes The different modes of operation and EEPROM informat

Page 11 - ±100 ppm) signal to derive

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 19 of 42Fused Memory DataWhen no EEPROM is detected at startup, the AT2LPenu

Page 12

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 2 of 42ApplicationsThe CY7C68300C/301C and CY7C68320C/321A implementa USB 2.

Page 13 - [+] Feedback

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 20 of 42MfgCBThe mfg_load and mfg_read vendor-specific commands arepassed do

Page 14

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 21 of 42EEPROM OrganizationThe contents of the recommended 256-byte (2048-bi

Page 15

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 22 of 42Table 11.Configuration Data Organization ByteAddressConfigurationIte

Page 16

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 23 of 42SRST Enable Bit 1Determines if the AT2LP is to do an SRST reset duri

Page 17

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 24 of 420x08 BUTTON_MODE Bit 7Button mode (100-pin package only). Sets ATAPU

Page 18

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 25 of 420x0A ReservedGPIO Output Pin StateBits 7:6Reserved. Must be set to z

Page 19

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 26 of 420x12 bcdUSB (LSB) USB Specification release number in BCD 0x000x13 b

Page 20 - MfgCB Byte Description Bits

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 27 of 420x32 iConfiguration Index to the configuration string. This entry mu

Page 21

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 28 of 420x4F bAlternateSetting Alternate setting 0x000x50 bNumEndpoints Numb

Page 22

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 29 of 420x75 Report_Size 8 bits 0x750x76 0x080x77 Report_Count 2 fields 0x95

Page 23

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 3 of 42Pin DiagramsThe AT2LP is available in different package types to meet

Page 24

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 30 of 420x95 bRecipient Identifier of the target recipientIf Recipient type

Page 25

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 31 of 420xB5 bString Unicode character LSB ’ ’ 0x200xB6 bString Unicode char

Page 26

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 32 of 420xDF bString Unicode character LSB ’ ’ 0x200xE0 bString Unicode char

Page 27

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 33 of 42Note: More than 0X100 bytes of configuration are shown for example o

Page 28

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 34 of 42Legal values for wValue are as follows: • 0x0000 Internal Config byt

Page 29

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 35 of 42Absolute Maximum RatingsStorage Temperature ...

Page 30

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 36 of 42AC Electrical CharacteristicsATA Timing CharacteristicsThe ATA inter

Page 31

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 37 of 42Package DiagramsFigure 12. 100-Pin Thin Plastic Quad Flatpack (14 x

Page 32

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 38 of 42Figure 13. 56-lead Shrunk Small Outline Package 056Package Diagrams

Page 33

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 39 of 42General PCB Layout Recommendations For USB Mass Storage DesignsThe f

Page 34

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 4 of 42Figure 3. 56-pin QFN Pinout (CY7C68300C/CY7C68301C)RESET#GNDARESET#D

Page 35

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 40 of 42Quad Flat Package No Leads (QFN) Package Design NotesElectrical cont

Page 36

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 41 of 42© Cypress Semiconductor Corporation, 2006. The information contained

Page 37

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 42 of 42Document History PagedDescription Title: CY7C68300C/CY7C68301C/CY7C6

Page 38

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 5 of 42Figure 4. 56-pin SSOP Pinout (CY7C68320C/CY7C68321C)5678910111213141

Page 39 - 51-85144 *F

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 6 of 42Figure 5. 56-pin QFN Pinout (CY7C68320C/CY7C68321C)GNDVCCGPIO2 GNDD

Page 40 - Other Design Considerations

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 7 of 42Figure 6. 100-pin TQFP Pinout (CY7C68320C/CY7C68321C only)1009998979

Page 41

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 8 of 42Pin DescriptionsThe following table lists the pinouts for the 56-pin

Page 42

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321CDocument 001-05809 Rev. *A Page 9 of 4230 16 23 SDA IO Data signal for I2C interface. (See “SCL, SDA” on pag

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