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Laboratory manual for TSEA44
Olle Seger, Per Karlström, Andreas Ehliar
Computer Engineering
Department of Electrical Engineering
Linköping University, S-581 83 Linköping, Sweden
Email: [email protected], perk@isy.liu.se, ehliar@isy.liu.se
October 28, 2014
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Page 1 - Laboratory manual for TSEA44

Laboratory manual for TSEA44Olle Seger, Per Karlström, Andreas EhliarComputer EngineeringDepartment of Electrical EngineeringLinköping University, S-5

Page 2

10CHAPTER 1. THE SYST EMDeviceSystemGatesCLB(1 CLB = 4 slices = Max 128 bits)MultiplierBlocksSelectRAM BlocksDCMsMax I/OPads(1)ArrayRow x Col. SlicesM

Page 3 - Contents

1.3. OPEN RISC11Global Clock MuxDCM DCM IOBCLBProgrammable I/OsBlock SelectRAM MultiplierConfigurable LogicFigure 1.3: Virtex-II architectural overvie

Page 4 - CONTENTS

12CHAPTER 1. THE SYST EMLUTFXGinputsFXINA MUXFXFXINBDFF/LATQREVDCECLKSRBYBXCECLKSRYDYYQF5MUXF5XLUTFinputsDFF/LATQREVDCECLKSRDXXQa) b)Figure 1.4: a) Vi

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1.3. OPEN RISC13WishboneOR1200 CPUMem Ctrl4kBRAM4kBROMUARTParportMaster SlaveEther Ctrl23721001Debug3JTAGPS24VGA5SRAMSRAM1

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14CHAPTER 1. THE SYST EMThe OR1200 CPU, [8], consists of several blocks:• High Performance 32-Bit CPU/DSP– 32-bit architecture implementing ORBIS32 in

Page 7 - The system

1.3. OPEN RISC15slave. Furthermore tristate is not used, instead there are two databuses, one in eachdirection. The address bus and the data busses ar

Page 8 - 1.2 Hardware

16CHAPTER 1. THE SYST EMThe Ethernet IP Core is capable of operating at 10 or 100 Mbps for Ethernet andFast Ethernet applications. An external PHY is

Page 9 - 1.2. HARDWARE

1.4. SOFTWARE17Command Explanationd <addr> display memory contentm <addr> <data> modify memory contentg <addr> go (execute)l l

Page 10 - 1.2.3 Virtex-II 4000 FPGA

18CHAPTER 1. THE SYST EMListing 1.2: Makefile for simpleprog (Listing 1.1)# The na me o f t h e p rog ram we w ant t o c o m pi l ePROGRAM = s i m p l

Page 11 - 1.3 Open RISC

1.4. SOFTWARE19Listing 1.3: Link script for simpleprog (Listing 1.1)MEMORY{vec tors : ORIGIN = 0 x00000000 , LENGTH = 0 x000020 00sdram : ORIGIN = 0 x

Page 13 - 1.3.3 OR1200 CPU

20CHAPTER 1. THE SYST EMThe simulator can also be started in an interactive mode byor32-uclinux-sim -f sim.cfg -i prog .In Figure 1.8 we show as an ex

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1.4. SOFTWARE21The command help will list the built-in shell commands.An important file is /etc/rc, the start-up file, which is shown in Listing 1.4. If

Page 15 - 1.3.6 Ethernet Controller

22CHAPTER 1. THE SYST EMListing 1.5: Program showing contents of a special purpose register.# i n c l u d e < s y s / t y p e s . h># i n c l u

Page 16 - 1.4 Software

Chapter 2Lab task 0 - Build a UART inVerilog2.1 IntroductionIn this introductory lab exercise you will learn the HDL Verilog. We r equire that youare

Page 17 - 1.4. SOFTWARE

24CHAPTER 2. LAB TASK 0 - BUILD A UART IN VERILOG2.2.2 The hardwareThe system clock is running at 40 MHz. You will need a reset-signal and a send-sign

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2.2. A SIMPLE UART25Listing 2.1: Test bench for the UART.‘ t i m e s c a l e 1 n s / 10 psmodule l a b 0 _ t b ( ) ;re g c l k _ i ;re g r s t _ i ;re

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26CHAPTER 2. LAB TASK 0 - BUILD A UART IN VERILOG2.3 ExercisesPreparation task 1Draw a HW diagram of the UART. Use simple components like counters, re

Page 20 - 1.4.4 µClinux

2.4. GTKTERM USAGE27/ / b l u e DIP s w i t c hNET "switch_i <7>" LOC = "AL3" ; / / SWITCH 1NET "switch_i <6>&quo

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28CHAPTER 2. LAB TASK 0 - BUILD A UART IN VERILOG

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Chapter 3Lab task 1 - Interfacing to theWishbone bus3.1 IntroductionIn this lab exercise you will get acquainted with the OR 1200 RISC processor andpa

Page 23 - Lab task 0 - Build a UART in

Contents1 The system 71.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.2 Hardware . . . . . . . . . . . . . . . . . .

Page 24 - 2.2.3 A simple testbench

30CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUS4. simulate the computer running the benchmark program.5. design a module containing hardware

Page 25 - 2.2. A SIMPLE UART

3.2. SOME BASIC FACTS ON THE WISHBONE BUS313. The Master deasserts the wb.stb, wb.cyc and wb.we-signals.4. The slave deasserts the wb.ack-signal.For t

Page 26 - Laboration task 1

32CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUSIn the return path the addressed slave’s s-bus is connected to all the masters. Thisis handle

Page 27 - 2.4 gtkterm usage

3.3. A SIMPLE COMPUTER33ControlUnitControlUnit>=1 txSRsendRSregrx_full F/Fwrtxtx_empty F/FshiftShiftRegrdin&&wb.stbwb.stbwb.wewb.sel[3]wb.d

Page 28

34CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUS7 0 071523319000_0000123459000_00004sel[0]sel[1]sel[2]sel[3]a) b)tx_empty rx_fullrx_fulltx_em

Page 29 - Wishbone bus

3.3. A SIMPLE COMPUTER35Check mon2.c to see what the monitor does at startup so that you can verify thatthe hardware does the correct thing.3.3.4 Test

Page 30 - Master Slave

36CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUS3.4 A Benchmark Program3.4.1 JPEG CompressionWe will use the first part, DCT, of the JPEG comp

Page 31 - 3.2.1 A Wishbone Interconnect

3.4. A BENCHMARK PROGRAM37Sofar we have presented three ways of computing the 2-D DCT. We compare thecomputation complexity of the algorithms:Algorith

Page 32 - 3.3 A Simple Computer

38CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUSPreparation task 5Why do we go through all the trouble inserting the module in Figure 3.8? Wh

Page 33 - Preparation task 2

3.5. DESIGN A PERFORMANCE COUNTER MODULE393. contain four 32 bit counters that can be read and written on the addresses 0x9900_0000to 0x9900_000c.4. T

Page 34 - Preparation task 4

4CONTENTS3.3 A Simple Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . .

Page 35 - Laboration task 2

40CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUS3.6 Useful CommandsWe have prepared a makefile based build system that is responsible for both

Page 36 - 3.4 A Benchmark Program

3.7. HOW TO GET STARTED WRITING/EXECUTING C PROGRAMS41• synthdir/foo.syr: Synthesis report• synthdir/foo_map.mrp: Map report• synthdir/foo.par: Place

Page 37 - 3.4. A BENCHMARK PROGRAM

42CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUSmacros shown in Listing 3.5 to access memory mapped I/O. These macros are definedin both the m

Page 38 - Preparation task 5

Chapter 4Lab task 2 - Design a JPEGaccelerator4.1 The lab systemIn this lab task you will learn how to build a hardware accelerator for the JPEG image

Page 39 - Laboration task 3

44CHAPTER 4. LAB TASK 2 - DESIGN A JPEG ACCELERATOR...DCT2 Control UnitcsrDCT648x16=12832NC32 NCRAMin8x12=96t_wrt_rd8x12=96WBCtrlTransposeMemoryBlock1

Page 40 - 3.6 Useful Commands

4.2. PROPOSED ARCHITECTURE45to use a block RAM is, in our opinion, to instantiate a library primitive. The code inListing 4.1 instantiates a block RAM

Page 41 - 3.7.1 A Note on Volatile

46CHAPTER 4. LAB TASK 2 - DESIGN A JPEG ACCELERATORwi r e [ 7 : 0 ] d a t a _ i , d a t a _ o ;wi r e [ 3 : 0 ] a d d r_a , a d d r _ b ;/ / 1 c o m b

Page 42

4.3. INTRODUCTION TOµCLINUX47Laboration task 4Design and implement the DCT accelerator with a WB interface.Laboration task 5Write a testbench for your

Page 43 - Lab task 2 - Design a JPEG

48CHAPTER 4. LAB TASK 2 - DESIGN A JPEG ACCELERATORservers to be left af ter you log out since this would prohibit other lab groups fromstarting a TFT

Page 44 - Preparation task 6

4.4. INTRODUCTION TO JPEGFILES49• jpegtest.c contains the test program we will use• testbild.raw is a grayscale image in raw format.• perfctr.c,perfct

Page 45 - 4.2.2 Distributed RAMs

CONTENTS56 Lab task 4 - Custom Instructions 616.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616.1.1 Huffman Coding .

Page 46 - Preparation task 7

50CHAPTER 4. LAB TASK 2 - DESIGN A JPEG ACCELERATOR4.4.2 The jpegtest applicationThis is the main test application we are going to use in the lab seri

Page 47 - Laboration task 6

4.6. QUANTIZATION510 0.5 1 1.5 2 2.5x 10400.20.40.60.811.21.41.61.8dmadct(N)read(N) Q(N) huff(N)ACCCPUclockcyclesFigure 4.3: Timestamps for JPEG compr

Page 48 - 4.4 Introduction to jpegfiles

52CHAPTER 4. LAB TASK 2 - DESIGN A JPEG ACCELERATORshifting 17 steps:Y [u, v] = round(A[u, v] − 8192 · δ[u, v]) · R[u, v] · 2−17=−96 −3

Page 49 - Preparation task 8

4.7. TIPS AND TRICKS534.7 Tips and tricksIn this section we have collected some notes that you might find useful.• If you want to simulate the 2D DCT a

Page 50 - 4.5 Timestamps

54CHAPTER 4. LAB TASK 2 - DESIGN A JPEG ACCELERATOR

Page 51 - 4.6 Quantization

Chapter 5Lab task 35.1 DMA in the DCT AcceleratorIn this lab we will improve the DCT accelerator by using DMA. You can find a speci-fication on how to d

Page 52 - Preparation task 9

56CHAPTER 5. LAB TASK 3IDLEWAITREADYGETBLOCKWAITREADY_LAST RELEASEBUSFigure 5.1: The proposed state diagram for the DMA accelerator.In Figure 5.1 ther

Page 53 - 4.7 Tips and tricks

5.1. DMA IN THE DCT ACCELERATOR57• dma_bram_data:The data we want to write to inmem in jpeg_top.• dma_bram_addr:The address we want to write the data

Page 54

58CHAPTER 5. LAB TASK 3It is important to note that the DCT accelerator should still work as before if DMAis not in use. But you are (of course) allow

Page 55 - Lab task 3

5.2. WHAT TO INCLUDE IN THE LAB REPORT595.2 What to Include in the Lab ReportThe lab report should contain all source code that you have written. (The

Page 57

60CHAPTER 5. LAB TASK 3WBCtrlAddressGenerator...DCT2 Control UnitcsrDCT6432NCNCRAMin8x12=96t_wrt_rd8x12=96TransposeMemoryBlock132dma_bram_addrdma_bram

Page 58 - Laboration task 12

Chapter 6Lab task 4 - Custom Instructions6.1 IntroductionIn this lab task you will learn how to design and integrate a new instruction into theprocess

Page 59

62CHAPTER 6. LAB TASK 4 - CUSTOM INSTRUCTIONSsuggests four Huffman tables. Two for the luminance, one for the DC values and onefor the AC values. And

Page 60 - CHAPTER 5. LAB TASK 3

6.3. PROPOSED ARCHITECTURE63tions in software. We will add a new group of special purpose registers to the pro-cessor, therefore we must make some cha

Page 61 - Chapter 6

64CHAPTER 6. LAB TASK 4 - CUSTOM INSTRUCTIONS6.3.2 Data PathThe data path unit should defined in theor1200_vlx_dpmodule, a stub can be found infile or12

Page 62 - 6.2 Adding a New Instruction

6.5. SOFTWARE IMPLEMENTATION65purpose register space in group 24 (the gr oup is selected with bit 15 - 11 of a specialpurpose register address), the t

Page 63 - 6.3 Proposed Architecture

66CHAPTER 6. LAB TASK 4 - CUSTOM INSTRUCTIONS: o u t p u t o p e r a n d s: i n p u t o p e r a n d s: l i s t o f c l o b b e r e d r e g i s t e r s

Page 64 - 6.4 Hardware Implementation

6.5. SOFTWARE IMPLEMENTATION676.5.2 Integration into jpegfilesWhen you find that the hardware is working and you have written some test programsto verif

Page 65 - 6.5 Software Implementation

68CHAPTER 6. LAB TASK 4 - CUSTOM INSTRUCTIONSCode Name Explanation Stands Alone0xF F C0 SOF0Start of frame for baseline coded pictures. No0xF F E0 APP

Page 66

6.8. WHAT TO INCLUDE IN THE LAB REPORT69• How to read from a special purpose registers with address 0xC000 in C-code:asm volatile("l.mfspr %0,%1,

Page 67 - Laboration task 14

Chapter 1The system1.1 IntroductionThis text is intended as a laboratory compendium for the course TSEA44 ComputerHardware - a System On a Chip. We be

Page 68 - 6.7 Tips and tricks

70CHAPTER 6. LAB TASK 4 - CUSTOM INSTRUCTIONS• What was bad?• What can we improve for the next year?• Do you have any other ideas for this course?• Di

Page 69

Bibliography[1] Xilinx Virtex-II Development Kit, www.avnet.com[2] Communications/Memory Module User’s Guide, www.avnet.com[3] Per Karlström,Mikael An

Page 71 - Bibliography

Appendix AOpen RISC Reference PlatformThis is the ORP standard memory map. The actual memory map for our system is insection 1.4.1.A.1 Address mapStar

Page 72 - BIBLIOGRAPHY

74APPENDIX A. OPEN RISC REFERENCE PLATFORMA.2 InterruptsNumber Peripheral0 Reserved1 Reserved2 UART16550 Controller3 General-Purpose I/O4 Ethernet Con

Page 73 - Open RISC Reference Platform

Appendix BThe Wishbone specificationB.1 IntroductionThe Wishbone specification basically dictates the interfaces and how they should behave. Themethod o

Page 74 - A.2 Interrupts

76APPENDIX B. THE WISHBONE SPECIFICATIONTable B.1: Wishbone signals (named from the master side).Name Direction Width Descriptionadr M->S 32 Addres

Page 75 - The Wishbone specification

B.3. WISHBONE CLASSICAL CYCLES77B.2.6 cycThis signal indicates that a valid bus cycle is in progress. This signal should be asserted for theduration o

Page 76 - B.2 Interface signals

78APPENDIX B. THE WISHBONE SPECIFICATION−WSS−CLK_IADR_ODAT_ODAT_IWE_OSEL_OSTB_OCYC_OACK_IVALIDVALIDVALIDMaster signalsFigure B.3: Wishbone classical s

Page 77 - −WSS−CLK_I

B.5. SYSTEM VERILOG INTERFACE79Table B.2: cti and bte signal valuesSignal group Value Descriptioncti 000 Classic cycle001 Constant address burst cycle

Page 78

8CHAPTER 1. THE SYST EMFigure 1.1: Block diagram of the Avnet main board.1.2 Hardware1.2.1 Virtex-II Development boardIn the course we will use a deve

Page 79 - B.5 System Verilog Interface

80APPENDIX B. THE WISHBONE SPECIFICATIONd a t _ t d a t _ i ; / / r e a d d a t a bu sl o g i c s t b ; / / s t r o b el o g i c cy c ; / / c y c l e

Page 80

Appendix CTips & TrixIn this appendix we have collected a number of tips and trix that you might find useful.• If you encounter some weird problems

Page 81 - Tips & Trix

82APPENDIX C. TIPS & TRIX• If you cannot find certain commands, make sure that the following commands arepresent in your .bashrc:source /opt/Xilinx

Page 82 - APPENDIX C. TIPS & TRIX

1.2. HARDWARE9AvBus Connectors (x2)1MByteSRAM (x32)CypressCY7C1041V3316MBytesFLASH (x32)MicronMT28F640J3A64MBytesSDRAM (x32)MicronMT48LC16M16A2PCMCIA1

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