Cypress Perform CY7C1380F Manuel d'utilisateur

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382F 18-Mbit (512K x 36/1M x 18)Pipelined SRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose,

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 10 of 34Truth TableThe Truth Table for this data sheet follows.[4, 5, 6, 7,

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 11 of 34Truth Table for Read/Write [4, 9]Function (CY7C1380D/CY7C1380F) GW B

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 12 of 34IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1380D/CY7C1382D incor

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 13 of 34When the TAP controller is in the Capture-IR state, the two leastsig

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 14 of 34when the EXTEST is entered as the current instruction. WhenHIGH, it

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 15 of 343.3V TAP AC Test ConditionsInput pulse levels...

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 16 of 34Identification Register DefinitionsInstruction FieldCY7C1380D/CY7C13

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 17 of 34119-Ball BGA Boundary Scan Order[14, 15] Bit # Ball ID Bit # Ball ID

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 18 of 34165-Ball BGA Boundary Scan Order[14, 16]Bit # Ball ID Bit # Ball ID

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 19 of 34Maximum RatingsExceeding the maximum ratings may impair the useful l

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 2 of 34Logic Block Diagram – CY7C1380D/CY7C1380F [3] (512K x 36)Logic Block

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 20 of 34Capacitance [19]Parameter Description Test Conditions100 TQFPPackage

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 21 of 34Figure 9. AC Test Loads and WaveformsOUTPUTR = 317ΩR = 351Ω5pFINCLU

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 22 of 34Switching Characteristics Over the Operating Range [20, 21]Parameter

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 23 of 34Switching Waveforms Figure 10. Read Cycle Timing [26]tCYCtCLCLKADSP

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 24 of 34Figure 11. Write Cycle Timing [26, 27]Switching Waveforms (continu

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 25 of 34Figure 12. Read/Write Cycle Timing [26, 28, 29]Switching Waveforms

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 26 of 34Figure 13. ZZ Mode Timing [30, 31]Switching Waveforms (continued)t

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 27 of 34Ordering InformationThe following table lists all speed, package and

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 28 of 34Speed(MHz) Ordering CodePackageDiagramPart and Package TypeOperating

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 29 of 34Speed(MHz) Ordering CodePackageDiagramPart and Package TypeOperating

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 3 of 34Pin Configurations100-Pin TQFP Pinout (3-Chip Enable)Figure 1. CY7C1

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 30 of 34Package Diagrams Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 31 of 34Figure 15. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)Package Diagra

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 32 of 34Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)Package Diagr

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 33 of 34Document History PageDocument Title: CY7C1380D/CY7C1382D/CY7C1380F/C

Document #: 38-05543 Rev. *F Revised January 12, 2009 Page 34 of 34All products and company names mentioned in this document may be the trademarks of

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 4 of 34119-Ball BGA PinoutFigure 3. CY7C1380F (512K X 36)Figure 4. CY7C138

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 5 of 34165-Ball FBGA Pinout (3-Chip Enable)Figure 5. CY7C1380D/CY7C1380F (5

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 6 of 34Table 1. Pin DefinitionsName I/O DescriptionA0, A1, A Input-Synchron

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 7 of 34MODE Input-Static Selects burst order. When tied to GND selects linea

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 8 of 34Functional OverviewAll synchronous inputs pass through input register

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382FDocument #: 38-05543 Rev. *F Page 9 of 34Burst SequencesThe CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382Fprovides a